/* parsed class NVC1C0 */

#include "nvtypes.h"
#include "clc1c0.h"

#include <assert.h>
#include <stdio.h>
#include "util/macros.h"

struct nv_nvc1c0_SET_OBJECT {
    uint32_t class_id;
    uint32_t engine_id;
};

static inline void
__NVC1C0_SET_OBJECT(uint32_t *val_out, struct nv_nvc1c0_SET_OBJECT st)
{
    uint32_t val = 0;
    
    assert(st.class_id < (UINT64_C(1) << 16));
    val |= st.class_id << 0;
    
    assert(st.engine_id < (UINT64_C(1) << 5));
    val |= st.engine_id << 16;
    *val_out = val;
}

#define V_NVC1C0_SET_OBJECT(val, args...) { \
    struct nv_nvc1c0_SET_OBJECT __data = args; \
    __NVC1C0_SET_OBJECT(&val, __data); \
}

#define VA_NVC1C0_SET_OBJECT V_NVC1C0_SET_OBJECT

#define P_NVC1C0_SET_OBJECT(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_OBJECT(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_OBJECT, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_NO_OPERATION {
    uint32_t v;
};

static inline void
__NVC1C0_NO_OPERATION(uint32_t *val_out, struct nv_nvc1c0_NO_OPERATION st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_NO_OPERATION(val, args...) { \
    struct nv_nvc1c0_NO_OPERATION __data = { .v = (args) }; \
    __NVC1C0_NO_OPERATION(&val, __data); \
}

#define VA_NVC1C0_NO_OPERATION V_NVC1C0_NO_OPERATION

#define P_NVC1C0_NO_OPERATION(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_NO_OPERATION(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_NO_OPERATION, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_NOTIFY_A {
    uint32_t address_upper;
};

static inline void
__NVC1C0_SET_NOTIFY_A(uint32_t *val_out, struct nv_nvc1c0_SET_NOTIFY_A st)
{
    uint32_t val = 0;
    
    assert(st.address_upper < (UINT64_C(1) << 8));
    val |= st.address_upper << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_NOTIFY_A(val, args...) { \
    struct nv_nvc1c0_SET_NOTIFY_A __data = { .address_upper = (args) }; \
    __NVC1C0_SET_NOTIFY_A(&val, __data); \
}

#define VA_NVC1C0_SET_NOTIFY_A V_NVC1C0_SET_NOTIFY_A

#define P_NVC1C0_SET_NOTIFY_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_NOTIFY_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_NOTIFY_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_NOTIFY_B {
    uint32_t address_lower;
};

static inline void
__NVC1C0_SET_NOTIFY_B(uint32_t *val_out, struct nv_nvc1c0_SET_NOTIFY_B st)
{
    uint32_t val = 0;
    
    val |= st.address_lower;
    *val_out = val;
}

#define V_NVC1C0_SET_NOTIFY_B(val, args...) { \
    struct nv_nvc1c0_SET_NOTIFY_B __data = { .address_lower = (args) }; \
    __NVC1C0_SET_NOTIFY_B(&val, __data); \
}

#define VA_NVC1C0_SET_NOTIFY_B V_NVC1C0_SET_NOTIFY_B

#define P_NVC1C0_SET_NOTIFY_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_NOTIFY_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_NOTIFY_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_NOTIFY {
    uint32_t type;
};

static inline void
__NVC1C0_NOTIFY(uint32_t *val_out, struct nv_nvc1c0_NOTIFY st)
{
    uint32_t val = 0;
    
    val |= st.type;
    *val_out = val;
}

#define V_NVC1C0_NOTIFY(val, args...) { \
    UNUSED uint32_t TYPE_WRITE_ONLY = NVC1C0_NOTIFY_TYPE_WRITE_ONLY; \
    UNUSED uint32_t TYPE_WRITE_THEN_AWAKEN = NVC1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN; \
    struct nv_nvc1c0_NOTIFY __data = { .type = (args) }; \
    __NVC1C0_NOTIFY(&val, __data); \
}

#define VA_NVC1C0_NOTIFY V_NVC1C0_NOTIFY

#define P_NVC1C0_NOTIFY(push, args...) do { \
    UNUSED uint32_t TYPE_WRITE_ONLY = NVC1C0_NOTIFY_TYPE_WRITE_ONLY; \
    UNUSED uint32_t TYPE_WRITE_THEN_AWAKEN = NVC1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_NOTIFY(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_NOTIFY, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_WAIT_FOR_IDLE {
    uint32_t v;
};

static inline void
__NVC1C0_WAIT_FOR_IDLE(uint32_t *val_out, struct nv_nvc1c0_WAIT_FOR_IDLE st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_WAIT_FOR_IDLE(val, args...) { \
    struct nv_nvc1c0_WAIT_FOR_IDLE __data = { .v = (args) }; \
    __NVC1C0_WAIT_FOR_IDLE(&val, __data); \
}

#define VA_NVC1C0_WAIT_FOR_IDLE V_NVC1C0_WAIT_FOR_IDLE

#define P_NVC1C0_WAIT_FOR_IDLE(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_WAIT_FOR_IDLE(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_WAIT_FOR_IDLE, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_GLOBAL_RENDER_ENABLE_A {
    uint32_t offset_upper;
};

static inline void
__NVC1C0_SET_GLOBAL_RENDER_ENABLE_A(uint32_t *val_out, struct nv_nvc1c0_SET_GLOBAL_RENDER_ENABLE_A st)
{
    uint32_t val = 0;
    
    assert(st.offset_upper < (UINT64_C(1) << 8));
    val |= st.offset_upper << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_GLOBAL_RENDER_ENABLE_A(val, args...) { \
    struct nv_nvc1c0_SET_GLOBAL_RENDER_ENABLE_A __data = { .offset_upper = (args) }; \
    __NVC1C0_SET_GLOBAL_RENDER_ENABLE_A(&val, __data); \
}

#define VA_NVC1C0_SET_GLOBAL_RENDER_ENABLE_A V_NVC1C0_SET_GLOBAL_RENDER_ENABLE_A

#define P_NVC1C0_SET_GLOBAL_RENDER_ENABLE_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_GLOBAL_RENDER_ENABLE_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_GLOBAL_RENDER_ENABLE_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_GLOBAL_RENDER_ENABLE_B {
    uint32_t offset_lower;
};

static inline void
__NVC1C0_SET_GLOBAL_RENDER_ENABLE_B(uint32_t *val_out, struct nv_nvc1c0_SET_GLOBAL_RENDER_ENABLE_B st)
{
    uint32_t val = 0;
    
    val |= st.offset_lower;
    *val_out = val;
}

#define V_NVC1C0_SET_GLOBAL_RENDER_ENABLE_B(val, args...) { \
    struct nv_nvc1c0_SET_GLOBAL_RENDER_ENABLE_B __data = { .offset_lower = (args) }; \
    __NVC1C0_SET_GLOBAL_RENDER_ENABLE_B(&val, __data); \
}

#define VA_NVC1C0_SET_GLOBAL_RENDER_ENABLE_B V_NVC1C0_SET_GLOBAL_RENDER_ENABLE_B

#define P_NVC1C0_SET_GLOBAL_RENDER_ENABLE_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_GLOBAL_RENDER_ENABLE_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_GLOBAL_RENDER_ENABLE_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_GLOBAL_RENDER_ENABLE_C {
    uint32_t mode;
};

static inline void
__NVC1C0_SET_GLOBAL_RENDER_ENABLE_C(uint32_t *val_out, struct nv_nvc1c0_SET_GLOBAL_RENDER_ENABLE_C st)
{
    uint32_t val = 0;
    
    assert(st.mode < (UINT64_C(1) << 3));
    val |= st.mode << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_GLOBAL_RENDER_ENABLE_C(val, args...) { \
    UNUSED uint32_t MODE_FALSE = NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE; \
    UNUSED uint32_t MODE_TRUE = NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE; \
    UNUSED uint32_t MODE_CONDITIONAL = NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL; \
    UNUSED uint32_t MODE_RENDER_IF_EQUAL = NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL; \
    UNUSED uint32_t MODE_RENDER_IF_NOT_EQUAL = NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL; \
    struct nv_nvc1c0_SET_GLOBAL_RENDER_ENABLE_C __data = { .mode = (args) }; \
    __NVC1C0_SET_GLOBAL_RENDER_ENABLE_C(&val, __data); \
}

#define VA_NVC1C0_SET_GLOBAL_RENDER_ENABLE_C V_NVC1C0_SET_GLOBAL_RENDER_ENABLE_C

#define P_NVC1C0_SET_GLOBAL_RENDER_ENABLE_C(push, args...) do { \
    UNUSED uint32_t MODE_FALSE = NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE; \
    UNUSED uint32_t MODE_TRUE = NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE; \
    UNUSED uint32_t MODE_CONDITIONAL = NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL; \
    UNUSED uint32_t MODE_RENDER_IF_EQUAL = NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL; \
    UNUSED uint32_t MODE_RENDER_IF_NOT_EQUAL = NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_GLOBAL_RENDER_ENABLE_C(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_GLOBAL_RENDER_ENABLE_C, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SEND_GO_IDLE {
    uint32_t v;
};

static inline void
__NVC1C0_SEND_GO_IDLE(uint32_t *val_out, struct nv_nvc1c0_SEND_GO_IDLE st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SEND_GO_IDLE(val, args...) { \
    struct nv_nvc1c0_SEND_GO_IDLE __data = { .v = (args) }; \
    __NVC1C0_SEND_GO_IDLE(&val, __data); \
}

#define VA_NVC1C0_SEND_GO_IDLE V_NVC1C0_SEND_GO_IDLE

#define P_NVC1C0_SEND_GO_IDLE(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SEND_GO_IDLE(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SEND_GO_IDLE, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_PM_TRIGGER {
    uint32_t v;
};

static inline void
__NVC1C0_PM_TRIGGER(uint32_t *val_out, struct nv_nvc1c0_PM_TRIGGER st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_PM_TRIGGER(val, args...) { \
    struct nv_nvc1c0_PM_TRIGGER __data = { .v = (args) }; \
    __NVC1C0_PM_TRIGGER(&val, __data); \
}

#define VA_NVC1C0_PM_TRIGGER V_NVC1C0_PM_TRIGGER

#define P_NVC1C0_PM_TRIGGER(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_PM_TRIGGER(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_PM_TRIGGER, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_PM_TRIGGER_WFI {
    uint32_t v;
};

static inline void
__NVC1C0_PM_TRIGGER_WFI(uint32_t *val_out, struct nv_nvc1c0_PM_TRIGGER_WFI st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_PM_TRIGGER_WFI(val, args...) { \
    struct nv_nvc1c0_PM_TRIGGER_WFI __data = { .v = (args) }; \
    __NVC1C0_PM_TRIGGER_WFI(&val, __data); \
}

#define VA_NVC1C0_PM_TRIGGER_WFI V_NVC1C0_PM_TRIGGER_WFI

#define P_NVC1C0_PM_TRIGGER_WFI(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_PM_TRIGGER_WFI(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_PM_TRIGGER_WFI, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_FE_ATOMIC_SEQUENCE_BEGIN {
    uint32_t v;
};

static inline void
__NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN(uint32_t *val_out, struct nv_nvc1c0_FE_ATOMIC_SEQUENCE_BEGIN st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN(val, args...) { \
    struct nv_nvc1c0_FE_ATOMIC_SEQUENCE_BEGIN __data = { .v = (args) }; \
    __NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN(&val, __data); \
}

#define VA_NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN V_NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN

#define P_NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_FE_ATOMIC_SEQUENCE_END {
    uint32_t v;
};

static inline void
__NVC1C0_FE_ATOMIC_SEQUENCE_END(uint32_t *val_out, struct nv_nvc1c0_FE_ATOMIC_SEQUENCE_END st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_FE_ATOMIC_SEQUENCE_END(val, args...) { \
    struct nv_nvc1c0_FE_ATOMIC_SEQUENCE_END __data = { .v = (args) }; \
    __NVC1C0_FE_ATOMIC_SEQUENCE_END(&val, __data); \
}

#define VA_NVC1C0_FE_ATOMIC_SEQUENCE_END V_NVC1C0_FE_ATOMIC_SEQUENCE_END

#define P_NVC1C0_FE_ATOMIC_SEQUENCE_END(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_FE_ATOMIC_SEQUENCE_END(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_FE_ATOMIC_SEQUENCE_END, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_INSTRUMENTATION_METHOD_HEADER {
    uint32_t v;
};

static inline void
__NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER(uint32_t *val_out, struct nv_nvc1c0_SET_INSTRUMENTATION_METHOD_HEADER st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER(val, args...) { \
    struct nv_nvc1c0_SET_INSTRUMENTATION_METHOD_HEADER __data = { .v = (args) }; \
    __NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER(&val, __data); \
}

#define VA_NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER V_NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER

#define P_NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_INSTRUMENTATION_METHOD_DATA {
    uint32_t v;
};

static inline void
__NVC1C0_SET_INSTRUMENTATION_METHOD_DATA(uint32_t *val_out, struct nv_nvc1c0_SET_INSTRUMENTATION_METHOD_DATA st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_INSTRUMENTATION_METHOD_DATA(val, args...) { \
    struct nv_nvc1c0_SET_INSTRUMENTATION_METHOD_DATA __data = { .v = (args) }; \
    __NVC1C0_SET_INSTRUMENTATION_METHOD_DATA(&val, __data); \
}

#define VA_NVC1C0_SET_INSTRUMENTATION_METHOD_DATA V_NVC1C0_SET_INSTRUMENTATION_METHOD_DATA

#define P_NVC1C0_SET_INSTRUMENTATION_METHOD_DATA(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_INSTRUMENTATION_METHOD_DATA(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_INSTRUMENTATION_METHOD_DATA, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_LINE_LENGTH_IN {
    uint32_t value;
};

static inline void
__NVC1C0_LINE_LENGTH_IN(uint32_t *val_out, struct nv_nvc1c0_LINE_LENGTH_IN st)
{
    uint32_t val = 0;
    
    val |= st.value;
    *val_out = val;
}

#define V_NVC1C0_LINE_LENGTH_IN(val, args...) { \
    struct nv_nvc1c0_LINE_LENGTH_IN __data = { .value = (args) }; \
    __NVC1C0_LINE_LENGTH_IN(&val, __data); \
}

#define VA_NVC1C0_LINE_LENGTH_IN V_NVC1C0_LINE_LENGTH_IN

#define P_NVC1C0_LINE_LENGTH_IN(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_LINE_LENGTH_IN(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_LINE_LENGTH_IN, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_LINE_COUNT {
    uint32_t value;
};

static inline void
__NVC1C0_LINE_COUNT(uint32_t *val_out, struct nv_nvc1c0_LINE_COUNT st)
{
    uint32_t val = 0;
    
    val |= st.value;
    *val_out = val;
}

#define V_NVC1C0_LINE_COUNT(val, args...) { \
    struct nv_nvc1c0_LINE_COUNT __data = { .value = (args) }; \
    __NVC1C0_LINE_COUNT(&val, __data); \
}

#define VA_NVC1C0_LINE_COUNT V_NVC1C0_LINE_COUNT

#define P_NVC1C0_LINE_COUNT(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_LINE_COUNT(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_LINE_COUNT, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_OFFSET_OUT_UPPER {
    uint32_t value;
};

static inline void
__NVC1C0_OFFSET_OUT_UPPER(uint32_t *val_out, struct nv_nvc1c0_OFFSET_OUT_UPPER st)
{
    uint32_t val = 0;
    
    assert(st.value < (UINT64_C(1) << 17));
    val |= st.value << 0;
    *val_out = val;
}

#define V_NVC1C0_OFFSET_OUT_UPPER(val, args...) { \
    struct nv_nvc1c0_OFFSET_OUT_UPPER __data = { .value = (args) }; \
    __NVC1C0_OFFSET_OUT_UPPER(&val, __data); \
}

#define VA_NVC1C0_OFFSET_OUT_UPPER V_NVC1C0_OFFSET_OUT_UPPER

#define P_NVC1C0_OFFSET_OUT_UPPER(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_OFFSET_OUT_UPPER(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_OFFSET_OUT_UPPER, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_OFFSET_OUT {
    uint32_t value;
};

static inline void
__NVC1C0_OFFSET_OUT(uint32_t *val_out, struct nv_nvc1c0_OFFSET_OUT st)
{
    uint32_t val = 0;
    
    val |= st.value;
    *val_out = val;
}

#define V_NVC1C0_OFFSET_OUT(val, args...) { \
    struct nv_nvc1c0_OFFSET_OUT __data = { .value = (args) }; \
    __NVC1C0_OFFSET_OUT(&val, __data); \
}

#define VA_NVC1C0_OFFSET_OUT V_NVC1C0_OFFSET_OUT

#define P_NVC1C0_OFFSET_OUT(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_OFFSET_OUT(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_OFFSET_OUT, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_PITCH_OUT {
    uint32_t value;
};

static inline void
__NVC1C0_PITCH_OUT(uint32_t *val_out, struct nv_nvc1c0_PITCH_OUT st)
{
    uint32_t val = 0;
    
    val |= st.value;
    *val_out = val;
}

#define V_NVC1C0_PITCH_OUT(val, args...) { \
    struct nv_nvc1c0_PITCH_OUT __data = { .value = (args) }; \
    __NVC1C0_PITCH_OUT(&val, __data); \
}

#define VA_NVC1C0_PITCH_OUT V_NVC1C0_PITCH_OUT

#define P_NVC1C0_PITCH_OUT(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_PITCH_OUT(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_PITCH_OUT, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_DST_BLOCK_SIZE {
    uint32_t width;
    uint32_t height;
    uint32_t depth;
};

static inline void
__NVC1C0_SET_DST_BLOCK_SIZE(uint32_t *val_out, struct nv_nvc1c0_SET_DST_BLOCK_SIZE st)
{
    uint32_t val = 0;
    
    assert(st.width < (UINT64_C(1) << 4));
    val |= st.width << 0;
    
    assert(st.height < (UINT64_C(1) << 4));
    val |= st.height << 4;
    
    assert(st.depth < (UINT64_C(1) << 4));
    val |= st.depth << 8;
    *val_out = val;
}

#define V_NVC1C0_SET_DST_BLOCK_SIZE(val, args...) { \
    UNUSED uint32_t WIDTH_ONE_GOB = NVC1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB; \
    UNUSED uint32_t HEIGHT_ONE_GOB = NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB; \
    UNUSED uint32_t HEIGHT_TWO_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS; \
    UNUSED uint32_t HEIGHT_FOUR_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS; \
    UNUSED uint32_t HEIGHT_EIGHT_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS; \
    UNUSED uint32_t HEIGHT_SIXTEEN_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS; \
    UNUSED uint32_t HEIGHT_THIRTYTWO_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS; \
    UNUSED uint32_t DEPTH_ONE_GOB = NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB; \
    UNUSED uint32_t DEPTH_TWO_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS; \
    UNUSED uint32_t DEPTH_FOUR_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS; \
    UNUSED uint32_t DEPTH_EIGHT_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS; \
    UNUSED uint32_t DEPTH_SIXTEEN_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS; \
    UNUSED uint32_t DEPTH_THIRTYTWO_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS; \
    struct nv_nvc1c0_SET_DST_BLOCK_SIZE __data = args; \
    __NVC1C0_SET_DST_BLOCK_SIZE(&val, __data); \
}

#define VA_NVC1C0_SET_DST_BLOCK_SIZE V_NVC1C0_SET_DST_BLOCK_SIZE

#define P_NVC1C0_SET_DST_BLOCK_SIZE(push, args...) do { \
    UNUSED uint32_t WIDTH_ONE_GOB = NVC1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB; \
    UNUSED uint32_t HEIGHT_ONE_GOB = NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB; \
    UNUSED uint32_t HEIGHT_TWO_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS; \
    UNUSED uint32_t HEIGHT_FOUR_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS; \
    UNUSED uint32_t HEIGHT_EIGHT_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS; \
    UNUSED uint32_t HEIGHT_SIXTEEN_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS; \
    UNUSED uint32_t HEIGHT_THIRTYTWO_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS; \
    UNUSED uint32_t DEPTH_ONE_GOB = NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB; \
    UNUSED uint32_t DEPTH_TWO_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS; \
    UNUSED uint32_t DEPTH_FOUR_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS; \
    UNUSED uint32_t DEPTH_EIGHT_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS; \
    UNUSED uint32_t DEPTH_SIXTEEN_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS; \
    UNUSED uint32_t DEPTH_THIRTYTWO_GOBS = NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_DST_BLOCK_SIZE(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_DST_BLOCK_SIZE, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_DST_WIDTH {
    uint32_t v;
};

static inline void
__NVC1C0_SET_DST_WIDTH(uint32_t *val_out, struct nv_nvc1c0_SET_DST_WIDTH st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_DST_WIDTH(val, args...) { \
    struct nv_nvc1c0_SET_DST_WIDTH __data = { .v = (args) }; \
    __NVC1C0_SET_DST_WIDTH(&val, __data); \
}

#define VA_NVC1C0_SET_DST_WIDTH V_NVC1C0_SET_DST_WIDTH

#define P_NVC1C0_SET_DST_WIDTH(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_DST_WIDTH(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_DST_WIDTH, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_DST_HEIGHT {
    uint32_t v;
};

static inline void
__NVC1C0_SET_DST_HEIGHT(uint32_t *val_out, struct nv_nvc1c0_SET_DST_HEIGHT st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_DST_HEIGHT(val, args...) { \
    struct nv_nvc1c0_SET_DST_HEIGHT __data = { .v = (args) }; \
    __NVC1C0_SET_DST_HEIGHT(&val, __data); \
}

#define VA_NVC1C0_SET_DST_HEIGHT V_NVC1C0_SET_DST_HEIGHT

#define P_NVC1C0_SET_DST_HEIGHT(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_DST_HEIGHT(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_DST_HEIGHT, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_DST_DEPTH {
    uint32_t v;
};

static inline void
__NVC1C0_SET_DST_DEPTH(uint32_t *val_out, struct nv_nvc1c0_SET_DST_DEPTH st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_DST_DEPTH(val, args...) { \
    struct nv_nvc1c0_SET_DST_DEPTH __data = { .v = (args) }; \
    __NVC1C0_SET_DST_DEPTH(&val, __data); \
}

#define VA_NVC1C0_SET_DST_DEPTH V_NVC1C0_SET_DST_DEPTH

#define P_NVC1C0_SET_DST_DEPTH(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_DST_DEPTH(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_DST_DEPTH, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_DST_LAYER {
    uint32_t v;
};

static inline void
__NVC1C0_SET_DST_LAYER(uint32_t *val_out, struct nv_nvc1c0_SET_DST_LAYER st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_DST_LAYER(val, args...) { \
    struct nv_nvc1c0_SET_DST_LAYER __data = { .v = (args) }; \
    __NVC1C0_SET_DST_LAYER(&val, __data); \
}

#define VA_NVC1C0_SET_DST_LAYER V_NVC1C0_SET_DST_LAYER

#define P_NVC1C0_SET_DST_LAYER(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_DST_LAYER(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_DST_LAYER, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_DST_ORIGIN_BYTES_X {
    uint32_t v;
};

static inline void
__NVC1C0_SET_DST_ORIGIN_BYTES_X(uint32_t *val_out, struct nv_nvc1c0_SET_DST_ORIGIN_BYTES_X st)
{
    uint32_t val = 0;
    
    assert(st.v < (UINT64_C(1) << 21));
    val |= st.v << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_DST_ORIGIN_BYTES_X(val, args...) { \
    struct nv_nvc1c0_SET_DST_ORIGIN_BYTES_X __data = { .v = (args) }; \
    __NVC1C0_SET_DST_ORIGIN_BYTES_X(&val, __data); \
}

#define VA_NVC1C0_SET_DST_ORIGIN_BYTES_X V_NVC1C0_SET_DST_ORIGIN_BYTES_X

#define P_NVC1C0_SET_DST_ORIGIN_BYTES_X(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_DST_ORIGIN_BYTES_X(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_DST_ORIGIN_BYTES_X, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_DST_ORIGIN_SAMPLES_Y {
    uint32_t v;
};

static inline void
__NVC1C0_SET_DST_ORIGIN_SAMPLES_Y(uint32_t *val_out, struct nv_nvc1c0_SET_DST_ORIGIN_SAMPLES_Y st)
{
    uint32_t val = 0;
    
    assert(st.v < (UINT64_C(1) << 17));
    val |= st.v << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_DST_ORIGIN_SAMPLES_Y(val, args...) { \
    struct nv_nvc1c0_SET_DST_ORIGIN_SAMPLES_Y __data = { .v = (args) }; \
    __NVC1C0_SET_DST_ORIGIN_SAMPLES_Y(&val, __data); \
}

#define VA_NVC1C0_SET_DST_ORIGIN_SAMPLES_Y V_NVC1C0_SET_DST_ORIGIN_SAMPLES_Y

#define P_NVC1C0_SET_DST_ORIGIN_SAMPLES_Y(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_DST_ORIGIN_SAMPLES_Y(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_DST_ORIGIN_SAMPLES_Y, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_LAUNCH_DMA {
    uint32_t dst_memory_layout;
    uint32_t completion_type;
    uint32_t interrupt_type;
    uint32_t semaphore_struct_size;
    uint32_t reduction_enable;
    uint32_t reduction_op;
    uint32_t reduction_format;
    uint32_t sysmembar_disable;
};

static inline void
__NVC1C0_LAUNCH_DMA(uint32_t *val_out, struct nv_nvc1c0_LAUNCH_DMA st)
{
    uint32_t val = 0;
    
    assert(st.dst_memory_layout < (UINT64_C(1) << 1));
    val |= st.dst_memory_layout << 0;
    
    assert(st.completion_type < (UINT64_C(1) << 2));
    val |= st.completion_type << 4;
    
    assert(st.interrupt_type < (UINT64_C(1) << 2));
    val |= st.interrupt_type << 8;
    
    assert(st.semaphore_struct_size < (UINT64_C(1) << 1));
    val |= st.semaphore_struct_size << 12;
    
    assert(st.reduction_enable < (UINT64_C(1) << 1));
    val |= st.reduction_enable << 1;
    
    assert(st.reduction_op < (UINT64_C(1) << 3));
    val |= st.reduction_op << 13;
    
    assert(st.reduction_format < (UINT64_C(1) << 2));
    val |= st.reduction_format << 2;
    
    assert(st.sysmembar_disable < (UINT64_C(1) << 1));
    val |= st.sysmembar_disable << 6;
    *val_out = val;
}

#define V_NVC1C0_LAUNCH_DMA(val, args...) { \
    UNUSED uint32_t DST_MEMORY_LAYOUT_BLOCKLINEAR = NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR; \
    UNUSED uint32_t DST_MEMORY_LAYOUT_PITCH = NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH; \
    UNUSED uint32_t COMPLETION_TYPE_FLUSH_DISABLE = NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE; \
    UNUSED uint32_t COMPLETION_TYPE_FLUSH_ONLY = NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY; \
    UNUSED uint32_t COMPLETION_TYPE_RELEASE_SEMAPHORE = NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE; \
    UNUSED uint32_t INTERRUPT_TYPE_NONE = NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE; \
    UNUSED uint32_t INTERRUPT_TYPE_INTERRUPT = NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT; \
    UNUSED uint32_t SEMAPHORE_STRUCT_SIZE_FOUR_WORDS = NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS; \
    UNUSED uint32_t SEMAPHORE_STRUCT_SIZE_ONE_WORD = NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD; \
    UNUSED uint32_t REDUCTION_ENABLE_FALSE = NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE; \
    UNUSED uint32_t REDUCTION_ENABLE_TRUE = NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE; \
    UNUSED uint32_t REDUCTION_OP_RED_ADD = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD; \
    UNUSED uint32_t REDUCTION_OP_RED_MIN = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN; \
    UNUSED uint32_t REDUCTION_OP_RED_MAX = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX; \
    UNUSED uint32_t REDUCTION_OP_RED_INC = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC; \
    UNUSED uint32_t REDUCTION_OP_RED_DEC = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC; \
    UNUSED uint32_t REDUCTION_OP_RED_AND = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND; \
    UNUSED uint32_t REDUCTION_OP_RED_OR = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR; \
    UNUSED uint32_t REDUCTION_OP_RED_XOR = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR; \
    UNUSED uint32_t REDUCTION_FORMAT_UNSIGNED_32 = NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32; \
    UNUSED uint32_t REDUCTION_FORMAT_SIGNED_32 = NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32; \
    UNUSED uint32_t SYSMEMBAR_DISABLE_FALSE = NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE; \
    UNUSED uint32_t SYSMEMBAR_DISABLE_TRUE = NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE; \
    struct nv_nvc1c0_LAUNCH_DMA __data = args; \
    __NVC1C0_LAUNCH_DMA(&val, __data); \
}

#define VA_NVC1C0_LAUNCH_DMA V_NVC1C0_LAUNCH_DMA

#define P_NVC1C0_LAUNCH_DMA(push, args...) do { \
    UNUSED uint32_t DST_MEMORY_LAYOUT_BLOCKLINEAR = NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR; \
    UNUSED uint32_t DST_MEMORY_LAYOUT_PITCH = NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH; \
    UNUSED uint32_t COMPLETION_TYPE_FLUSH_DISABLE = NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE; \
    UNUSED uint32_t COMPLETION_TYPE_FLUSH_ONLY = NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY; \
    UNUSED uint32_t COMPLETION_TYPE_RELEASE_SEMAPHORE = NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE; \
    UNUSED uint32_t INTERRUPT_TYPE_NONE = NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE; \
    UNUSED uint32_t INTERRUPT_TYPE_INTERRUPT = NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT; \
    UNUSED uint32_t SEMAPHORE_STRUCT_SIZE_FOUR_WORDS = NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS; \
    UNUSED uint32_t SEMAPHORE_STRUCT_SIZE_ONE_WORD = NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD; \
    UNUSED uint32_t REDUCTION_ENABLE_FALSE = NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE; \
    UNUSED uint32_t REDUCTION_ENABLE_TRUE = NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE; \
    UNUSED uint32_t REDUCTION_OP_RED_ADD = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD; \
    UNUSED uint32_t REDUCTION_OP_RED_MIN = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN; \
    UNUSED uint32_t REDUCTION_OP_RED_MAX = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX; \
    UNUSED uint32_t REDUCTION_OP_RED_INC = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC; \
    UNUSED uint32_t REDUCTION_OP_RED_DEC = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC; \
    UNUSED uint32_t REDUCTION_OP_RED_AND = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND; \
    UNUSED uint32_t REDUCTION_OP_RED_OR = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR; \
    UNUSED uint32_t REDUCTION_OP_RED_XOR = NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR; \
    UNUSED uint32_t REDUCTION_FORMAT_UNSIGNED_32 = NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32; \
    UNUSED uint32_t REDUCTION_FORMAT_SIGNED_32 = NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32; \
    UNUSED uint32_t SYSMEMBAR_DISABLE_FALSE = NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE; \
    UNUSED uint32_t SYSMEMBAR_DISABLE_TRUE = NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_LAUNCH_DMA(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_LAUNCH_DMA, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_LOAD_INLINE_DATA {
    uint32_t v;
};

static inline void
__NVC1C0_LOAD_INLINE_DATA(uint32_t *val_out, struct nv_nvc1c0_LOAD_INLINE_DATA st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_LOAD_INLINE_DATA(val, args...) { \
    struct nv_nvc1c0_LOAD_INLINE_DATA __data = { .v = (args) }; \
    __NVC1C0_LOAD_INLINE_DATA(&val, __data); \
}

#define VA_NVC1C0_LOAD_INLINE_DATA V_NVC1C0_LOAD_INLINE_DATA

#define P_NVC1C0_LOAD_INLINE_DATA(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_LOAD_INLINE_DATA(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_LOAD_INLINE_DATA, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_I2M_SEMAPHORE_A {
    uint32_t offset_upper;
};

static inline void
__NVC1C0_SET_I2M_SEMAPHORE_A(uint32_t *val_out, struct nv_nvc1c0_SET_I2M_SEMAPHORE_A st)
{
    uint32_t val = 0;
    
    assert(st.offset_upper < (UINT64_C(1) << 8));
    val |= st.offset_upper << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_I2M_SEMAPHORE_A(val, args...) { \
    struct nv_nvc1c0_SET_I2M_SEMAPHORE_A __data = { .offset_upper = (args) }; \
    __NVC1C0_SET_I2M_SEMAPHORE_A(&val, __data); \
}

#define VA_NVC1C0_SET_I2M_SEMAPHORE_A V_NVC1C0_SET_I2M_SEMAPHORE_A

#define P_NVC1C0_SET_I2M_SEMAPHORE_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_I2M_SEMAPHORE_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_I2M_SEMAPHORE_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_I2M_SEMAPHORE_B {
    uint32_t offset_lower;
};

static inline void
__NVC1C0_SET_I2M_SEMAPHORE_B(uint32_t *val_out, struct nv_nvc1c0_SET_I2M_SEMAPHORE_B st)
{
    uint32_t val = 0;
    
    val |= st.offset_lower;
    *val_out = val;
}

#define V_NVC1C0_SET_I2M_SEMAPHORE_B(val, args...) { \
    struct nv_nvc1c0_SET_I2M_SEMAPHORE_B __data = { .offset_lower = (args) }; \
    __NVC1C0_SET_I2M_SEMAPHORE_B(&val, __data); \
}

#define VA_NVC1C0_SET_I2M_SEMAPHORE_B V_NVC1C0_SET_I2M_SEMAPHORE_B

#define P_NVC1C0_SET_I2M_SEMAPHORE_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_I2M_SEMAPHORE_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_I2M_SEMAPHORE_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_I2M_SEMAPHORE_C {
    uint32_t payload;
};

static inline void
__NVC1C0_SET_I2M_SEMAPHORE_C(uint32_t *val_out, struct nv_nvc1c0_SET_I2M_SEMAPHORE_C st)
{
    uint32_t val = 0;
    
    val |= st.payload;
    *val_out = val;
}

#define V_NVC1C0_SET_I2M_SEMAPHORE_C(val, args...) { \
    struct nv_nvc1c0_SET_I2M_SEMAPHORE_C __data = { .payload = (args) }; \
    __NVC1C0_SET_I2M_SEMAPHORE_C(&val, __data); \
}

#define VA_NVC1C0_SET_I2M_SEMAPHORE_C V_NVC1C0_SET_I2M_SEMAPHORE_C

#define P_NVC1C0_SET_I2M_SEMAPHORE_C(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_I2M_SEMAPHORE_C(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_I2M_SEMAPHORE_C, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_I2M_SPARE_NOOP00 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_I2M_SPARE_NOOP00(uint32_t *val_out, struct nv_nvc1c0_SET_I2M_SPARE_NOOP00 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_I2M_SPARE_NOOP00(val, args...) { \
    struct nv_nvc1c0_SET_I2M_SPARE_NOOP00 __data = { .v = (args) }; \
    __NVC1C0_SET_I2M_SPARE_NOOP00(&val, __data); \
}

#define VA_NVC1C0_SET_I2M_SPARE_NOOP00 V_NVC1C0_SET_I2M_SPARE_NOOP00

#define P_NVC1C0_SET_I2M_SPARE_NOOP00(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_I2M_SPARE_NOOP00(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_I2M_SPARE_NOOP00, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_I2M_SPARE_NOOP01 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_I2M_SPARE_NOOP01(uint32_t *val_out, struct nv_nvc1c0_SET_I2M_SPARE_NOOP01 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_I2M_SPARE_NOOP01(val, args...) { \
    struct nv_nvc1c0_SET_I2M_SPARE_NOOP01 __data = { .v = (args) }; \
    __NVC1C0_SET_I2M_SPARE_NOOP01(&val, __data); \
}

#define VA_NVC1C0_SET_I2M_SPARE_NOOP01 V_NVC1C0_SET_I2M_SPARE_NOOP01

#define P_NVC1C0_SET_I2M_SPARE_NOOP01(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_I2M_SPARE_NOOP01(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_I2M_SPARE_NOOP01, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_I2M_SPARE_NOOP02 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_I2M_SPARE_NOOP02(uint32_t *val_out, struct nv_nvc1c0_SET_I2M_SPARE_NOOP02 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_I2M_SPARE_NOOP02(val, args...) { \
    struct nv_nvc1c0_SET_I2M_SPARE_NOOP02 __data = { .v = (args) }; \
    __NVC1C0_SET_I2M_SPARE_NOOP02(&val, __data); \
}

#define VA_NVC1C0_SET_I2M_SPARE_NOOP02 V_NVC1C0_SET_I2M_SPARE_NOOP02

#define P_NVC1C0_SET_I2M_SPARE_NOOP02(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_I2M_SPARE_NOOP02(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_I2M_SPARE_NOOP02, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_I2M_SPARE_NOOP03 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_I2M_SPARE_NOOP03(uint32_t *val_out, struct nv_nvc1c0_SET_I2M_SPARE_NOOP03 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_I2M_SPARE_NOOP03(val, args...) { \
    struct nv_nvc1c0_SET_I2M_SPARE_NOOP03 __data = { .v = (args) }; \
    __NVC1C0_SET_I2M_SPARE_NOOP03(&val, __data); \
}

#define VA_NVC1C0_SET_I2M_SPARE_NOOP03 V_NVC1C0_SET_I2M_SPARE_NOOP03

#define P_NVC1C0_SET_I2M_SPARE_NOOP03(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_I2M_SPARE_NOOP03(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_I2M_SPARE_NOOP03, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_VALID_SPAN_OVERFLOW_AREA_A {
    uint32_t address_upper;
};

static inline void
__NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A(uint32_t *val_out, struct nv_nvc1c0_SET_VALID_SPAN_OVERFLOW_AREA_A st)
{
    uint32_t val = 0;
    
    assert(st.address_upper < (UINT64_C(1) << 8));
    val |= st.address_upper << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A(val, args...) { \
    struct nv_nvc1c0_SET_VALID_SPAN_OVERFLOW_AREA_A __data = { .address_upper = (args) }; \
    __NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A(&val, __data); \
}

#define VA_NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A V_NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A

#define P_NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_VALID_SPAN_OVERFLOW_AREA_B {
    uint32_t address_lower;
};

static inline void
__NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B(uint32_t *val_out, struct nv_nvc1c0_SET_VALID_SPAN_OVERFLOW_AREA_B st)
{
    uint32_t val = 0;
    
    val |= st.address_lower;
    *val_out = val;
}

#define V_NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B(val, args...) { \
    struct nv_nvc1c0_SET_VALID_SPAN_OVERFLOW_AREA_B __data = { .address_lower = (args) }; \
    __NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B(&val, __data); \
}

#define VA_NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B V_NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B

#define P_NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_VALID_SPAN_OVERFLOW_AREA_C {
    uint32_t size;
};

static inline void
__NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C(uint32_t *val_out, struct nv_nvc1c0_SET_VALID_SPAN_OVERFLOW_AREA_C st)
{
    uint32_t val = 0;
    
    val |= st.size;
    *val_out = val;
}

#define V_NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C(val, args...) { \
    struct nv_nvc1c0_SET_VALID_SPAN_OVERFLOW_AREA_C __data = { .size = (args) }; \
    __NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C(&val, __data); \
}

#define VA_NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C V_NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C

#define P_NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_COALESCE_WAITING_PERIOD_UNIT {
    uint32_t clocks;
};

static inline void
__NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT(uint32_t *val_out, struct nv_nvc1c0_SET_COALESCE_WAITING_PERIOD_UNIT st)
{
    uint32_t val = 0;
    
    val |= st.clocks;
    *val_out = val;
}

#define V_NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT(val, args...) { \
    struct nv_nvc1c0_SET_COALESCE_WAITING_PERIOD_UNIT __data = { .clocks = (args) }; \
    __NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT(&val, __data); \
}

#define VA_NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT V_NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT

#define P_NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_PERFMON_TRANSFER {
    uint32_t v;
};

static inline void
__NVC1C0_PERFMON_TRANSFER(uint32_t *val_out, struct nv_nvc1c0_PERFMON_TRANSFER st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_PERFMON_TRANSFER(val, args...) { \
    struct nv_nvc1c0_PERFMON_TRANSFER __data = { .v = (args) }; \
    __NVC1C0_PERFMON_TRANSFER(&val, __data); \
}

#define VA_NVC1C0_PERFMON_TRANSFER V_NVC1C0_PERFMON_TRANSFER

#define P_NVC1C0_PERFMON_TRANSFER(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_PERFMON_TRANSFER(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_PERFMON_TRANSFER, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_SHARED_MEMORY_WINDOW {
    uint32_t base_address;
};

static inline void
__NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_SHARED_MEMORY_WINDOW st)
{
    uint32_t val = 0;
    
    val |= st.base_address;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_SHARED_MEMORY_WINDOW __data = { .base_address = (args) }; \
    __NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW V_NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW

#define P_NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SELECT_MAXWELL_TEXTURE_HEADERS {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS(uint32_t *val_out, struct nv_nvc1c0_SET_SELECT_MAXWELL_TEXTURE_HEADERS st)
{
    uint32_t val = 0;
    
    assert(st.v < (UINT64_C(1) << 1));
    val |= st.v << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS(val, args...) { \
    UNUSED uint32_t V_FALSE = NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE; \
    UNUSED uint32_t V_TRUE = NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE; \
    struct nv_nvc1c0_SET_SELECT_MAXWELL_TEXTURE_HEADERS __data = { .v = (args) }; \
    __NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS(&val, __data); \
}

#define VA_NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS V_NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS

#define P_NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS(push, args...) do { \
    UNUSED uint32_t V_FALSE = NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE; \
    UNUSED uint32_t V_TRUE = NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_INVALIDATE_SHADER_CACHES {
    uint32_t instruction;
    uint32_t data;
    uint32_t constant;
    uint32_t locks;
    uint32_t flush_data;
};

static inline void
__NVC1C0_INVALIDATE_SHADER_CACHES(uint32_t *val_out, struct nv_nvc1c0_INVALIDATE_SHADER_CACHES st)
{
    uint32_t val = 0;
    
    assert(st.instruction < (UINT64_C(1) << 1));
    val |= st.instruction << 0;
    
    assert(st.data < (UINT64_C(1) << 1));
    val |= st.data << 4;
    
    assert(st.constant < (UINT64_C(1) << 1));
    val |= st.constant << 12;
    
    assert(st.locks < (UINT64_C(1) << 1));
    val |= st.locks << 1;
    
    assert(st.flush_data < (UINT64_C(1) << 1));
    val |= st.flush_data << 2;
    *val_out = val;
}

#define V_NVC1C0_INVALIDATE_SHADER_CACHES(val, args...) { \
    UNUSED uint32_t INSTRUCTION_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE; \
    UNUSED uint32_t INSTRUCTION_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE; \
    UNUSED uint32_t DATA_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE; \
    UNUSED uint32_t DATA_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE; \
    UNUSED uint32_t CONSTANT_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE; \
    UNUSED uint32_t CONSTANT_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE; \
    UNUSED uint32_t LOCKS_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE; \
    UNUSED uint32_t LOCKS_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE; \
    UNUSED uint32_t FLUSH_DATA_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE; \
    UNUSED uint32_t FLUSH_DATA_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE; \
    struct nv_nvc1c0_INVALIDATE_SHADER_CACHES __data = args; \
    __NVC1C0_INVALIDATE_SHADER_CACHES(&val, __data); \
}

#define VA_NVC1C0_INVALIDATE_SHADER_CACHES V_NVC1C0_INVALIDATE_SHADER_CACHES

#define P_NVC1C0_INVALIDATE_SHADER_CACHES(push, args...) do { \
    UNUSED uint32_t INSTRUCTION_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE; \
    UNUSED uint32_t INSTRUCTION_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE; \
    UNUSED uint32_t DATA_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE; \
    UNUSED uint32_t DATA_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE; \
    UNUSED uint32_t CONSTANT_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE; \
    UNUSED uint32_t CONSTANT_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE; \
    UNUSED uint32_t LOCKS_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE; \
    UNUSED uint32_t LOCKS_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE; \
    UNUSED uint32_t FLUSH_DATA_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE; \
    UNUSED uint32_t FLUSH_DATA_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_INVALIDATE_SHADER_CACHES(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_INVALIDATE_SHADER_CACHES, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD00 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD00(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD00 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD00(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD00 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD00(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD00 V_NVC1C0_SET_RESERVED_SW_METHOD00

#define P_NVC1C0_SET_RESERVED_SW_METHOD00(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD00(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD00, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD01 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD01(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD01 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD01(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD01 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD01(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD01 V_NVC1C0_SET_RESERVED_SW_METHOD01

#define P_NVC1C0_SET_RESERVED_SW_METHOD01(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD01(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD01, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD02 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD02(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD02 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD02(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD02 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD02(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD02 V_NVC1C0_SET_RESERVED_SW_METHOD02

#define P_NVC1C0_SET_RESERVED_SW_METHOD02(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD02(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD02, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD03 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD03(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD03 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD03(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD03 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD03(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD03 V_NVC1C0_SET_RESERVED_SW_METHOD03

#define P_NVC1C0_SET_RESERVED_SW_METHOD03(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD03(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD03, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD04 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD04(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD04 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD04(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD04 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD04(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD04 V_NVC1C0_SET_RESERVED_SW_METHOD04

#define P_NVC1C0_SET_RESERVED_SW_METHOD04(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD04(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD04, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD05 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD05(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD05 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD05(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD05 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD05(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD05 V_NVC1C0_SET_RESERVED_SW_METHOD05

#define P_NVC1C0_SET_RESERVED_SW_METHOD05(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD05(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD05, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD06 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD06(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD06 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD06(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD06 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD06(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD06 V_NVC1C0_SET_RESERVED_SW_METHOD06

#define P_NVC1C0_SET_RESERVED_SW_METHOD06(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD06(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD06, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD07 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD07(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD07 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD07(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD07 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD07(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD07 V_NVC1C0_SET_RESERVED_SW_METHOD07

#define P_NVC1C0_SET_RESERVED_SW_METHOD07(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD07(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD07, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_CWD_CONTROL {
    uint32_t sm_selection;
};

static inline void
__NVC1C0_SET_CWD_CONTROL(uint32_t *val_out, struct nv_nvc1c0_SET_CWD_CONTROL st)
{
    uint32_t val = 0;
    
    assert(st.sm_selection < (UINT64_C(1) << 1));
    val |= st.sm_selection << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_CWD_CONTROL(val, args...) { \
    UNUSED uint32_t SM_SELECTION_LOAD_BALANCED = NVC1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED; \
    UNUSED uint32_t SM_SELECTION_ROUND_ROBIN = NVC1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN; \
    struct nv_nvc1c0_SET_CWD_CONTROL __data = { .sm_selection = (args) }; \
    __NVC1C0_SET_CWD_CONTROL(&val, __data); \
}

#define VA_NVC1C0_SET_CWD_CONTROL V_NVC1C0_SET_CWD_CONTROL

#define P_NVC1C0_SET_CWD_CONTROL(push, args...) do { \
    UNUSED uint32_t SM_SELECTION_LOAD_BALANCED = NVC1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED; \
    UNUSED uint32_t SM_SELECTION_ROUND_ROBIN = NVC1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_CWD_CONTROL(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_CWD_CONTROL, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI {
    uint32_t lines;
    uint32_t tag;
};

static inline void
__NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI(uint32_t *val_out, struct nv_nvc1c0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI st)
{
    uint32_t val = 0;
    
    assert(st.lines < (UINT64_C(1) << 1));
    val |= st.lines << 0;
    
    assert(st.tag < (UINT64_C(1) << 22));
    val |= st.tag << 4;
    *val_out = val;
}

#define V_NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI(val, args...) { \
    UNUSED uint32_t LINES_ALL = NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL; \
    UNUSED uint32_t LINES_ONE = NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE; \
    struct nv_nvc1c0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI __data = args; \
    __NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI(&val, __data); \
}

#define VA_NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI V_NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI

#define P_NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI(push, args...) do { \
    UNUSED uint32_t LINES_ALL = NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL; \
    UNUSED uint32_t LINES_ONE = NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_CWD_REF_COUNTER {
    uint32_t select;
    uint32_t value;
};

static inline void
__NVC1C0_SET_CWD_REF_COUNTER(uint32_t *val_out, struct nv_nvc1c0_SET_CWD_REF_COUNTER st)
{
    uint32_t val = 0;
    
    assert(st.select < (UINT64_C(1) << 6));
    val |= st.select << 0;
    
    assert(st.value < (UINT64_C(1) << 16));
    val |= st.value << 8;
    *val_out = val;
}

#define V_NVC1C0_SET_CWD_REF_COUNTER(val, args...) { \
    struct nv_nvc1c0_SET_CWD_REF_COUNTER __data = args; \
    __NVC1C0_SET_CWD_REF_COUNTER(&val, __data); \
}

#define VA_NVC1C0_SET_CWD_REF_COUNTER V_NVC1C0_SET_CWD_REF_COUNTER

#define P_NVC1C0_SET_CWD_REF_COUNTER(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_CWD_REF_COUNTER(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_CWD_REF_COUNTER, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD08 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD08(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD08 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD08(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD08 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD08(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD08 V_NVC1C0_SET_RESERVED_SW_METHOD08

#define P_NVC1C0_SET_RESERVED_SW_METHOD08(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD08(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD08, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD09 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD09(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD09 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD09(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD09 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD09(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD09 V_NVC1C0_SET_RESERVED_SW_METHOD09

#define P_NVC1C0_SET_RESERVED_SW_METHOD09(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD09(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD09, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD10 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD10(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD10 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD10(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD10 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD10(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD10 V_NVC1C0_SET_RESERVED_SW_METHOD10

#define P_NVC1C0_SET_RESERVED_SW_METHOD10(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD10(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD10, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD11 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD11(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD11 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD11(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD11 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD11(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD11 V_NVC1C0_SET_RESERVED_SW_METHOD11

#define P_NVC1C0_SET_RESERVED_SW_METHOD11(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD11(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD11, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD12 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD12(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD12 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD12(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD12 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD12(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD12 V_NVC1C0_SET_RESERVED_SW_METHOD12

#define P_NVC1C0_SET_RESERVED_SW_METHOD12(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD12(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD12, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD13 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD13(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD13 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD13(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD13 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD13(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD13 V_NVC1C0_SET_RESERVED_SW_METHOD13

#define P_NVC1C0_SET_RESERVED_SW_METHOD13(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD13(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD13, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD14 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD14(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD14 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD14(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD14 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD14(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD14 V_NVC1C0_SET_RESERVED_SW_METHOD14

#define P_NVC1C0_SET_RESERVED_SW_METHOD14(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD14(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD14, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RESERVED_SW_METHOD15 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_RESERVED_SW_METHOD15(uint32_t *val_out, struct nv_nvc1c0_SET_RESERVED_SW_METHOD15 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_RESERVED_SW_METHOD15(val, args...) { \
    struct nv_nvc1c0_SET_RESERVED_SW_METHOD15 __data = { .v = (args) }; \
    __NVC1C0_SET_RESERVED_SW_METHOD15(&val, __data); \
}

#define VA_NVC1C0_SET_RESERVED_SW_METHOD15 V_NVC1C0_SET_RESERVED_SW_METHOD15

#define P_NVC1C0_SET_RESERVED_SW_METHOD15(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RESERVED_SW_METHOD15(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RESERVED_SW_METHOD15, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_GWC_SCG_TYPE {
    uint32_t scg_type;
};

static inline void
__NVC1C0_SET_GWC_SCG_TYPE(uint32_t *val_out, struct nv_nvc1c0_SET_GWC_SCG_TYPE st)
{
    uint32_t val = 0;
    
    assert(st.scg_type < (UINT64_C(1) << 1));
    val |= st.scg_type << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_GWC_SCG_TYPE(val, args...) { \
    UNUSED uint32_t SCG_TYPE_GRAPHICS_COMPUTE0 = NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0; \
    UNUSED uint32_t SCG_TYPE_COMPUTE1 = NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1; \
    struct nv_nvc1c0_SET_GWC_SCG_TYPE __data = { .scg_type = (args) }; \
    __NVC1C0_SET_GWC_SCG_TYPE(&val, __data); \
}

#define VA_NVC1C0_SET_GWC_SCG_TYPE V_NVC1C0_SET_GWC_SCG_TYPE

#define P_NVC1C0_SET_GWC_SCG_TYPE(push, args...) do { \
    UNUSED uint32_t SCG_TYPE_GRAPHICS_COMPUTE0 = NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0; \
    UNUSED uint32_t SCG_TYPE_COMPUTE1 = NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_GWC_SCG_TYPE(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_GWC_SCG_TYPE, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SCG_CONTROL {
    uint32_t compute1_max_sm_count;
    uint32_t compute1_min_sm_count;
    uint32_t disable_compute1_limit_in_all_compute;
};

static inline void
__NVC1C0_SET_SCG_CONTROL(uint32_t *val_out, struct nv_nvc1c0_SET_SCG_CONTROL st)
{
    uint32_t val = 0;
    
    assert(st.compute1_max_sm_count < (UINT64_C(1) << 9));
    val |= st.compute1_max_sm_count << 0;
    
    assert(st.compute1_min_sm_count < (UINT64_C(1) << 9));
    val |= st.compute1_min_sm_count << 12;
    
    assert(st.disable_compute1_limit_in_all_compute < (UINT64_C(1) << 1));
    val |= st.disable_compute1_limit_in_all_compute << 24;
    *val_out = val;
}

#define V_NVC1C0_SET_SCG_CONTROL(val, args...) { \
    UNUSED uint32_t DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE = NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE; \
    UNUSED uint32_t DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE = NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE; \
    struct nv_nvc1c0_SET_SCG_CONTROL __data = args; \
    __NVC1C0_SET_SCG_CONTROL(&val, __data); \
}

#define VA_NVC1C0_SET_SCG_CONTROL V_NVC1C0_SET_SCG_CONTROL

#define P_NVC1C0_SET_SCG_CONTROL(push, args...) do { \
    UNUSED uint32_t DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE = NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE; \
    UNUSED uint32_t DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE = NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SCG_CONTROL(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SCG_CONTROL, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_INVALIDATE_CONSTANT_BUFFER_CACHE_A {
    uint32_t address_upper;
};

static inline void
__NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A(uint32_t *val_out, struct nv_nvc1c0_INVALIDATE_CONSTANT_BUFFER_CACHE_A st)
{
    uint32_t val = 0;
    
    assert(st.address_upper < (UINT64_C(1) << 17));
    val |= st.address_upper << 0;
    *val_out = val;
}

#define V_NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A(val, args...) { \
    struct nv_nvc1c0_INVALIDATE_CONSTANT_BUFFER_CACHE_A __data = { .address_upper = (args) }; \
    __NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A(&val, __data); \
}

#define VA_NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A V_NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A

#define P_NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_INVALIDATE_CONSTANT_BUFFER_CACHE_B {
    uint32_t address_lower;
};

static inline void
__NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B(uint32_t *val_out, struct nv_nvc1c0_INVALIDATE_CONSTANT_BUFFER_CACHE_B st)
{
    uint32_t val = 0;
    
    val |= st.address_lower;
    *val_out = val;
}

#define V_NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B(val, args...) { \
    struct nv_nvc1c0_INVALIDATE_CONSTANT_BUFFER_CACHE_B __data = { .address_lower = (args) }; \
    __NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B(&val, __data); \
}

#define VA_NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B V_NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B

#define P_NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_INVALIDATE_CONSTANT_BUFFER_CACHE_C {
    uint32_t byte_count;
    uint32_t thru_l2;
};

static inline void
__NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C(uint32_t *val_out, struct nv_nvc1c0_INVALIDATE_CONSTANT_BUFFER_CACHE_C st)
{
    uint32_t val = 0;
    
    assert(st.byte_count < (UINT64_C(1) << 17));
    val |= st.byte_count << 0;
    
    assert(st.thru_l2 < (UINT64_C(1) << 1));
    val |= st.thru_l2 << 31;
    *val_out = val;
}

#define V_NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C(val, args...) { \
    UNUSED uint32_t THRU_L2_FALSE = NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE; \
    UNUSED uint32_t THRU_L2_TRUE = NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE; \
    struct nv_nvc1c0_INVALIDATE_CONSTANT_BUFFER_CACHE_C __data = args; \
    __NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C(&val, __data); \
}

#define VA_NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C V_NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C

#define P_NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C(push, args...) do { \
    UNUSED uint32_t THRU_L2_FALSE = NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE; \
    UNUSED uint32_t THRU_L2_TRUE = NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_COMPUTE_CLASS_VERSION {
    uint32_t current;
    uint32_t oldest_supported;
};

static inline void
__NVC1C0_SET_COMPUTE_CLASS_VERSION(uint32_t *val_out, struct nv_nvc1c0_SET_COMPUTE_CLASS_VERSION st)
{
    uint32_t val = 0;
    
    assert(st.current < (UINT64_C(1) << 16));
    val |= st.current << 0;
    
    assert(st.oldest_supported < (UINT64_C(1) << 16));
    val |= st.oldest_supported << 16;
    *val_out = val;
}

#define V_NVC1C0_SET_COMPUTE_CLASS_VERSION(val, args...) { \
    struct nv_nvc1c0_SET_COMPUTE_CLASS_VERSION __data = args; \
    __NVC1C0_SET_COMPUTE_CLASS_VERSION(&val, __data); \
}

#define VA_NVC1C0_SET_COMPUTE_CLASS_VERSION V_NVC1C0_SET_COMPUTE_CLASS_VERSION

#define P_NVC1C0_SET_COMPUTE_CLASS_VERSION(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_COMPUTE_CLASS_VERSION(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_COMPUTE_CLASS_VERSION, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_CHECK_COMPUTE_CLASS_VERSION {
    uint32_t current;
    uint32_t oldest_supported;
};

static inline void
__NVC1C0_CHECK_COMPUTE_CLASS_VERSION(uint32_t *val_out, struct nv_nvc1c0_CHECK_COMPUTE_CLASS_VERSION st)
{
    uint32_t val = 0;
    
    assert(st.current < (UINT64_C(1) << 16));
    val |= st.current << 0;
    
    assert(st.oldest_supported < (UINT64_C(1) << 16));
    val |= st.oldest_supported << 16;
    *val_out = val;
}

#define V_NVC1C0_CHECK_COMPUTE_CLASS_VERSION(val, args...) { \
    struct nv_nvc1c0_CHECK_COMPUTE_CLASS_VERSION __data = args; \
    __NVC1C0_CHECK_COMPUTE_CLASS_VERSION(&val, __data); \
}

#define VA_NVC1C0_CHECK_COMPUTE_CLASS_VERSION V_NVC1C0_CHECK_COMPUTE_CLASS_VERSION

#define P_NVC1C0_CHECK_COMPUTE_CLASS_VERSION(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_CHECK_COMPUTE_CLASS_VERSION(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_CHECK_COMPUTE_CLASS_VERSION, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_QMD_VERSION {
    uint32_t current;
    uint32_t oldest_supported;
};

static inline void
__NVC1C0_SET_QMD_VERSION(uint32_t *val_out, struct nv_nvc1c0_SET_QMD_VERSION st)
{
    uint32_t val = 0;
    
    assert(st.current < (UINT64_C(1) << 16));
    val |= st.current << 0;
    
    assert(st.oldest_supported < (UINT64_C(1) << 16));
    val |= st.oldest_supported << 16;
    *val_out = val;
}

#define V_NVC1C0_SET_QMD_VERSION(val, args...) { \
    struct nv_nvc1c0_SET_QMD_VERSION __data = args; \
    __NVC1C0_SET_QMD_VERSION(&val, __data); \
}

#define VA_NVC1C0_SET_QMD_VERSION V_NVC1C0_SET_QMD_VERSION

#define P_NVC1C0_SET_QMD_VERSION(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_QMD_VERSION(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_QMD_VERSION, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_WFI_CONFIG {
    uint32_t enable_scg_type_wfi;
};

static inline void
__NVC1C0_SET_WFI_CONFIG(uint32_t *val_out, struct nv_nvc1c0_SET_WFI_CONFIG st)
{
    uint32_t val = 0;
    
    assert(st.enable_scg_type_wfi < (UINT64_C(1) << 1));
    val |= st.enable_scg_type_wfi << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_WFI_CONFIG(val, args...) { \
    UNUSED uint32_t ENABLE_SCG_TYPE_WFI_FALSE = NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE; \
    UNUSED uint32_t ENABLE_SCG_TYPE_WFI_TRUE = NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE; \
    struct nv_nvc1c0_SET_WFI_CONFIG __data = { .enable_scg_type_wfi = (args) }; \
    __NVC1C0_SET_WFI_CONFIG(&val, __data); \
}

#define VA_NVC1C0_SET_WFI_CONFIG V_NVC1C0_SET_WFI_CONFIG

#define P_NVC1C0_SET_WFI_CONFIG(push, args...) do { \
    UNUSED uint32_t ENABLE_SCG_TYPE_WFI_FALSE = NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE; \
    UNUSED uint32_t ENABLE_SCG_TYPE_WFI_TRUE = NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_WFI_CONFIG(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_WFI_CONFIG, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_CHECK_QMD_VERSION {
    uint32_t current;
    uint32_t oldest_supported;
};

static inline void
__NVC1C0_CHECK_QMD_VERSION(uint32_t *val_out, struct nv_nvc1c0_CHECK_QMD_VERSION st)
{
    uint32_t val = 0;
    
    assert(st.current < (UINT64_C(1) << 16));
    val |= st.current << 0;
    
    assert(st.oldest_supported < (UINT64_C(1) << 16));
    val |= st.oldest_supported << 16;
    *val_out = val;
}

#define V_NVC1C0_CHECK_QMD_VERSION(val, args...) { \
    struct nv_nvc1c0_CHECK_QMD_VERSION __data = args; \
    __NVC1C0_CHECK_QMD_VERSION(&val, __data); \
}

#define VA_NVC1C0_CHECK_QMD_VERSION V_NVC1C0_CHECK_QMD_VERSION

#define P_NVC1C0_CHECK_QMD_VERSION(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_CHECK_QMD_VERSION(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_CHECK_QMD_VERSION, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_WAIT_FOR_IDLE_SCG_TYPE {
    uint32_t v;
};

static inline void
__NVC1C0_WAIT_FOR_IDLE_SCG_TYPE(uint32_t *val_out, struct nv_nvc1c0_WAIT_FOR_IDLE_SCG_TYPE st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_WAIT_FOR_IDLE_SCG_TYPE(val, args...) { \
    struct nv_nvc1c0_WAIT_FOR_IDLE_SCG_TYPE __data = { .v = (args) }; \
    __NVC1C0_WAIT_FOR_IDLE_SCG_TYPE(&val, __data); \
}

#define VA_NVC1C0_WAIT_FOR_IDLE_SCG_TYPE V_NVC1C0_WAIT_FOR_IDLE_SCG_TYPE

#define P_NVC1C0_WAIT_FOR_IDLE_SCG_TYPE(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_WAIT_FOR_IDLE_SCG_TYPE(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_WAIT_FOR_IDLE_SCG_TYPE, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_INVALIDATE_SKED_CACHES {
    uint32_t v;
};

static inline void
__NVC1C0_INVALIDATE_SKED_CACHES(uint32_t *val_out, struct nv_nvc1c0_INVALIDATE_SKED_CACHES st)
{
    uint32_t val = 0;
    
    assert(st.v < (UINT64_C(1) << 1));
    val |= st.v << 0;
    *val_out = val;
}

#define V_NVC1C0_INVALIDATE_SKED_CACHES(val, args...) { \
    struct nv_nvc1c0_INVALIDATE_SKED_CACHES __data = { .v = (args) }; \
    __NVC1C0_INVALIDATE_SKED_CACHES(&val, __data); \
}

#define VA_NVC1C0_INVALIDATE_SKED_CACHES V_NVC1C0_INVALIDATE_SKED_CACHES

#define P_NVC1C0_INVALIDATE_SKED_CACHES(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_INVALIDATE_SKED_CACHES(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_INVALIDATE_SKED_CACHES, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SCG_RENDER_ENABLE_CONTROL {
    uint32_t compute1_uses_render_enable;
};

static inline void
__NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL(uint32_t *val_out, struct nv_nvc1c0_SET_SCG_RENDER_ENABLE_CONTROL st)
{
    uint32_t val = 0;
    
    assert(st.compute1_uses_render_enable < (UINT64_C(1) << 1));
    val |= st.compute1_uses_render_enable << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL(val, args...) { \
    UNUSED uint32_t COMPUTE1_USES_RENDER_ENABLE_FALSE = NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE; \
    UNUSED uint32_t COMPUTE1_USES_RENDER_ENABLE_TRUE = NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE; \
    struct nv_nvc1c0_SET_SCG_RENDER_ENABLE_CONTROL __data = { .compute1_uses_render_enable = (args) }; \
    __NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL(&val, __data); \
}

#define VA_NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL V_NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL

#define P_NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL(push, args...) do { \
    UNUSED uint32_t COMPUTE1_USES_RENDER_ENABLE_FALSE = NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE; \
    UNUSED uint32_t COMPUTE1_USES_RENDER_ENABLE_TRUE = NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_SHARED_MEMORY_WINDOW_A {
    uint32_t base_address_upper;
};

static inline void
__NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_SHARED_MEMORY_WINDOW_A st)
{
    uint32_t val = 0;
    
    assert(st.base_address_upper < (UINT64_C(1) << 17));
    val |= st.base_address_upper << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_SHARED_MEMORY_WINDOW_A __data = { .base_address_upper = (args) }; \
    __NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A V_NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A

#define P_NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_SHARED_MEMORY_WINDOW_B {
    uint32_t base_address;
};

static inline void
__NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_SHARED_MEMORY_WINDOW_B st)
{
    uint32_t val = 0;
    
    val |= st.base_address;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_SHARED_MEMORY_WINDOW_B __data = { .base_address = (args) }; \
    __NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B V_NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B

#define P_NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SCG_HYSTERESIS_CONTROL {
    uint32_t use_timeout_once;
    uint32_t use_null_timeout_once;
};

static inline void
__NVC1C0_SCG_HYSTERESIS_CONTROL(uint32_t *val_out, struct nv_nvc1c0_SCG_HYSTERESIS_CONTROL st)
{
    uint32_t val = 0;
    
    assert(st.use_timeout_once < (UINT64_C(1) << 1));
    val |= st.use_timeout_once << 0;
    
    assert(st.use_null_timeout_once < (UINT64_C(1) << 1));
    val |= st.use_null_timeout_once << 1;
    *val_out = val;
}

#define V_NVC1C0_SCG_HYSTERESIS_CONTROL(val, args...) { \
    UNUSED uint32_t USE_TIMEOUT_ONCE_FALSE = NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE; \
    UNUSED uint32_t USE_TIMEOUT_ONCE_TRUE = NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE; \
    UNUSED uint32_t USE_NULL_TIMEOUT_ONCE_FALSE = NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE; \
    UNUSED uint32_t USE_NULL_TIMEOUT_ONCE_TRUE = NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE; \
    struct nv_nvc1c0_SCG_HYSTERESIS_CONTROL __data = args; \
    __NVC1C0_SCG_HYSTERESIS_CONTROL(&val, __data); \
}

#define VA_NVC1C0_SCG_HYSTERESIS_CONTROL V_NVC1C0_SCG_HYSTERESIS_CONTROL

#define P_NVC1C0_SCG_HYSTERESIS_CONTROL(push, args...) do { \
    UNUSED uint32_t USE_TIMEOUT_ONCE_FALSE = NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE; \
    UNUSED uint32_t USE_TIMEOUT_ONCE_TRUE = NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE; \
    UNUSED uint32_t USE_NULL_TIMEOUT_ONCE_FALSE = NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE; \
    UNUSED uint32_t USE_NULL_TIMEOUT_ONCE_TRUE = NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SCG_HYSTERESIS_CONTROL(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SCG_HYSTERESIS_CONTROL, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_CWD_SLOT_COUNT {
    uint32_t v;
};

static inline void
__NVC1C0_SET_CWD_SLOT_COUNT(uint32_t *val_out, struct nv_nvc1c0_SET_CWD_SLOT_COUNT st)
{
    uint32_t val = 0;
    
    assert(st.v < (UINT64_C(1) << 8));
    val |= st.v << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_CWD_SLOT_COUNT(val, args...) { \
    struct nv_nvc1c0_SET_CWD_SLOT_COUNT __data = { .v = (args) }; \
    __NVC1C0_SET_CWD_SLOT_COUNT(&val, __data); \
}

#define VA_NVC1C0_SET_CWD_SLOT_COUNT V_NVC1C0_SET_CWD_SLOT_COUNT

#define P_NVC1C0_SET_CWD_SLOT_COUNT(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_CWD_SLOT_COUNT(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_CWD_SLOT_COUNT, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SEND_PCAS_A {
    uint32_t qmd_address_shifted8;
};

static inline void
__NVC1C0_SEND_PCAS_A(uint32_t *val_out, struct nv_nvc1c0_SEND_PCAS_A st)
{
    uint32_t val = 0;
    
    val |= st.qmd_address_shifted8;
    *val_out = val;
}

#define V_NVC1C0_SEND_PCAS_A(val, args...) { \
    struct nv_nvc1c0_SEND_PCAS_A __data = { .qmd_address_shifted8 = (args) }; \
    __NVC1C0_SEND_PCAS_A(&val, __data); \
}

#define VA_NVC1C0_SEND_PCAS_A V_NVC1C0_SEND_PCAS_A

#define P_NVC1C0_SEND_PCAS_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SEND_PCAS_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SEND_PCAS_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SEND_PCAS_B {
    uint32_t from;
    uint32_t delta;
};

static inline void
__NVC1C0_SEND_PCAS_B(uint32_t *val_out, struct nv_nvc1c0_SEND_PCAS_B st)
{
    uint32_t val = 0;
    
    assert(st.from < (UINT64_C(1) << 24));
    val |= st.from << 0;
    
    assert(st.delta < (UINT64_C(1) << 8));
    val |= st.delta << 24;
    *val_out = val;
}

#define V_NVC1C0_SEND_PCAS_B(val, args...) { \
    struct nv_nvc1c0_SEND_PCAS_B __data = args; \
    __NVC1C0_SEND_PCAS_B(&val, __data); \
}

#define VA_NVC1C0_SEND_PCAS_B V_NVC1C0_SEND_PCAS_B

#define P_NVC1C0_SEND_PCAS_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SEND_PCAS_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SEND_PCAS_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SEND_SIGNALING_PCAS_B {
    uint32_t invalidate;
    uint32_t schedule;
};

static inline void
__NVC1C0_SEND_SIGNALING_PCAS_B(uint32_t *val_out, struct nv_nvc1c0_SEND_SIGNALING_PCAS_B st)
{
    uint32_t val = 0;
    
    assert(st.invalidate < (UINT64_C(1) << 1));
    val |= st.invalidate << 0;
    
    assert(st.schedule < (UINT64_C(1) << 1));
    val |= st.schedule << 1;
    *val_out = val;
}

#define V_NVC1C0_SEND_SIGNALING_PCAS_B(val, args...) { \
    UNUSED uint32_t INVALIDATE_FALSE = NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE; \
    UNUSED uint32_t INVALIDATE_TRUE = NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE; \
    UNUSED uint32_t SCHEDULE_FALSE = NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE; \
    UNUSED uint32_t SCHEDULE_TRUE = NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE; \
    struct nv_nvc1c0_SEND_SIGNALING_PCAS_B __data = args; \
    __NVC1C0_SEND_SIGNALING_PCAS_B(&val, __data); \
}

#define VA_NVC1C0_SEND_SIGNALING_PCAS_B V_NVC1C0_SEND_SIGNALING_PCAS_B

#define P_NVC1C0_SEND_SIGNALING_PCAS_B(push, args...) do { \
    UNUSED uint32_t INVALIDATE_FALSE = NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE; \
    UNUSED uint32_t INVALIDATE_TRUE = NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE; \
    UNUSED uint32_t SCHEDULE_FALSE = NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE; \
    UNUSED uint32_t SCHEDULE_TRUE = NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SEND_SIGNALING_PCAS_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SEND_SIGNALING_PCAS_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A {
    uint32_t size_upper;
};

static inline void
__NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A st)
{
    uint32_t val = 0;
    
    assert(st.size_upper < (UINT64_C(1) << 8));
    val |= st.size_upper << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A __data = { .size_upper = (args) }; \
    __NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A V_NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A

#define P_NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B {
    uint32_t size_lower;
};

static inline void
__NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B st)
{
    uint32_t val = 0;
    
    val |= st.size_lower;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B __data = { .size_lower = (args) }; \
    __NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B V_NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B

#define P_NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C {
    uint32_t max_sm_count;
};

static inline void
__NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C st)
{
    uint32_t val = 0;
    
    assert(st.max_sm_count < (UINT64_C(1) << 9));
    val |= st.max_sm_count << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C __data = { .max_sm_count = (args) }; \
    __NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C V_NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C

#define P_NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A {
    uint32_t size_upper;
};

static inline void
__NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A st)
{
    uint32_t val = 0;
    
    assert(st.size_upper < (UINT64_C(1) << 8));
    val |= st.size_upper << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A __data = { .size_upper = (args) }; \
    __NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A V_NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A

#define P_NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B {
    uint32_t size_lower;
};

static inline void
__NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B st)
{
    uint32_t val = 0;
    
    val |= st.size_lower;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B __data = { .size_lower = (args) }; \
    __NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B V_NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B

#define P_NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C {
    uint32_t max_sm_count;
};

static inline void
__NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C st)
{
    uint32_t val = 0;
    
    assert(st.max_sm_count < (UINT64_C(1) << 9));
    val |= st.max_sm_count << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C __data = { .max_sm_count = (args) }; \
    __NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C V_NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C

#define P_NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPA_VERSION {
    uint32_t minor;
    uint32_t major;
};

static inline void
__NVC1C0_SET_SPA_VERSION(uint32_t *val_out, struct nv_nvc1c0_SET_SPA_VERSION st)
{
    uint32_t val = 0;
    
    assert(st.minor < (UINT64_C(1) << 8));
    val |= st.minor << 0;
    
    assert(st.major < (UINT64_C(1) << 8));
    val |= st.major << 8;
    *val_out = val;
}

#define V_NVC1C0_SET_SPA_VERSION(val, args...) { \
    struct nv_nvc1c0_SET_SPA_VERSION __data = args; \
    __NVC1C0_SET_SPA_VERSION(&val, __data); \
}

#define VA_NVC1C0_SET_SPA_VERSION V_NVC1C0_SET_SPA_VERSION

#define P_NVC1C0_SET_SPA_VERSION(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPA_VERSION(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPA_VERSION, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_INLINE_QMD_ADDRESS_A {
    uint32_t qmd_address_shifted8_upper;
};

static inline void
__NVC1C0_SET_INLINE_QMD_ADDRESS_A(uint32_t *val_out, struct nv_nvc1c0_SET_INLINE_QMD_ADDRESS_A st)
{
    uint32_t val = 0;
    
    val |= st.qmd_address_shifted8_upper;
    *val_out = val;
}

#define V_NVC1C0_SET_INLINE_QMD_ADDRESS_A(val, args...) { \
    struct nv_nvc1c0_SET_INLINE_QMD_ADDRESS_A __data = { .qmd_address_shifted8_upper = (args) }; \
    __NVC1C0_SET_INLINE_QMD_ADDRESS_A(&val, __data); \
}

#define VA_NVC1C0_SET_INLINE_QMD_ADDRESS_A V_NVC1C0_SET_INLINE_QMD_ADDRESS_A

#define P_NVC1C0_SET_INLINE_QMD_ADDRESS_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_INLINE_QMD_ADDRESS_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_INLINE_QMD_ADDRESS_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_INLINE_QMD_ADDRESS_B {
    uint32_t qmd_address_shifted8_lower;
};

static inline void
__NVC1C0_SET_INLINE_QMD_ADDRESS_B(uint32_t *val_out, struct nv_nvc1c0_SET_INLINE_QMD_ADDRESS_B st)
{
    uint32_t val = 0;
    
    val |= st.qmd_address_shifted8_lower;
    *val_out = val;
}

#define V_NVC1C0_SET_INLINE_QMD_ADDRESS_B(val, args...) { \
    struct nv_nvc1c0_SET_INLINE_QMD_ADDRESS_B __data = { .qmd_address_shifted8_lower = (args) }; \
    __NVC1C0_SET_INLINE_QMD_ADDRESS_B(&val, __data); \
}

#define VA_NVC1C0_SET_INLINE_QMD_ADDRESS_B V_NVC1C0_SET_INLINE_QMD_ADDRESS_B

#define P_NVC1C0_SET_INLINE_QMD_ADDRESS_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_INLINE_QMD_ADDRESS_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_INLINE_QMD_ADDRESS_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_LOAD_INLINE_QMD_DATA {
    uint32_t v;
};

static inline void
__NVC1C0_LOAD_INLINE_QMD_DATA(uint32_t *val_out, struct nv_nvc1c0_LOAD_INLINE_QMD_DATA st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_LOAD_INLINE_QMD_DATA(val, args...) { \
    struct nv_nvc1c0_LOAD_INLINE_QMD_DATA __data = { .v = (args) }; \
    __NVC1C0_LOAD_INLINE_QMD_DATA(&val, __data); \
}

#define VA_NVC1C0_LOAD_INLINE_QMD_DATA(i) V_NVC1C0_LOAD_INLINE_QMD_DATA

#define P_NVC1C0_LOAD_INLINE_QMD_DATA(push, idx, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_LOAD_INLINE_QMD_DATA(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_LOAD_INLINE_QMD_DATA(idx), nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON00 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON00(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON00 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON00(val, args...) { \
    struct nv_nvc1c0_SET_FALCON00 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON00(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON00 V_NVC1C0_SET_FALCON00

#define P_NVC1C0_SET_FALCON00(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON00(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON00, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON01 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON01(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON01 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON01(val, args...) { \
    struct nv_nvc1c0_SET_FALCON01 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON01(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON01 V_NVC1C0_SET_FALCON01

#define P_NVC1C0_SET_FALCON01(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON01(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON01, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON02 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON02(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON02 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON02(val, args...) { \
    struct nv_nvc1c0_SET_FALCON02 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON02(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON02 V_NVC1C0_SET_FALCON02

#define P_NVC1C0_SET_FALCON02(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON02(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON02, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON03 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON03(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON03 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON03(val, args...) { \
    struct nv_nvc1c0_SET_FALCON03 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON03(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON03 V_NVC1C0_SET_FALCON03

#define P_NVC1C0_SET_FALCON03(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON03(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON03, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON04 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON04(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON04 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON04(val, args...) { \
    struct nv_nvc1c0_SET_FALCON04 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON04(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON04 V_NVC1C0_SET_FALCON04

#define P_NVC1C0_SET_FALCON04(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON04(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON04, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON05 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON05(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON05 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON05(val, args...) { \
    struct nv_nvc1c0_SET_FALCON05 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON05(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON05 V_NVC1C0_SET_FALCON05

#define P_NVC1C0_SET_FALCON05(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON05(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON05, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON06 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON06(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON06 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON06(val, args...) { \
    struct nv_nvc1c0_SET_FALCON06 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON06(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON06 V_NVC1C0_SET_FALCON06

#define P_NVC1C0_SET_FALCON06(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON06(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON06, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON07 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON07(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON07 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON07(val, args...) { \
    struct nv_nvc1c0_SET_FALCON07 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON07(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON07 V_NVC1C0_SET_FALCON07

#define P_NVC1C0_SET_FALCON07(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON07(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON07, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON08 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON08(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON08 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON08(val, args...) { \
    struct nv_nvc1c0_SET_FALCON08 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON08(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON08 V_NVC1C0_SET_FALCON08

#define P_NVC1C0_SET_FALCON08(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON08(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON08, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON09 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON09(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON09 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON09(val, args...) { \
    struct nv_nvc1c0_SET_FALCON09 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON09(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON09 V_NVC1C0_SET_FALCON09

#define P_NVC1C0_SET_FALCON09(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON09(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON09, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON10 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON10(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON10 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON10(val, args...) { \
    struct nv_nvc1c0_SET_FALCON10 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON10(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON10 V_NVC1C0_SET_FALCON10

#define P_NVC1C0_SET_FALCON10(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON10(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON10, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON11 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON11(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON11 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON11(val, args...) { \
    struct nv_nvc1c0_SET_FALCON11 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON11(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON11 V_NVC1C0_SET_FALCON11

#define P_NVC1C0_SET_FALCON11(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON11(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON11, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON12 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON12(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON12 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON12(val, args...) { \
    struct nv_nvc1c0_SET_FALCON12 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON12(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON12 V_NVC1C0_SET_FALCON12

#define P_NVC1C0_SET_FALCON12(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON12(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON12, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON13 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON13(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON13 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON13(val, args...) { \
    struct nv_nvc1c0_SET_FALCON13 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON13(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON13 V_NVC1C0_SET_FALCON13

#define P_NVC1C0_SET_FALCON13(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON13(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON13, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON14 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON14(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON14 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON14(val, args...) { \
    struct nv_nvc1c0_SET_FALCON14 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON14(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON14 V_NVC1C0_SET_FALCON14

#define P_NVC1C0_SET_FALCON14(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON14(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON14, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON15 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON15(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON15 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON15(val, args...) { \
    struct nv_nvc1c0_SET_FALCON15 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON15(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON15 V_NVC1C0_SET_FALCON15

#define P_NVC1C0_SET_FALCON15(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON15(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON15, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON16 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON16(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON16 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON16(val, args...) { \
    struct nv_nvc1c0_SET_FALCON16 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON16(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON16 V_NVC1C0_SET_FALCON16

#define P_NVC1C0_SET_FALCON16(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON16(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON16, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON17 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON17(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON17 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON17(val, args...) { \
    struct nv_nvc1c0_SET_FALCON17 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON17(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON17 V_NVC1C0_SET_FALCON17

#define P_NVC1C0_SET_FALCON17(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON17(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON17, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON18 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON18(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON18 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON18(val, args...) { \
    struct nv_nvc1c0_SET_FALCON18 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON18(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON18 V_NVC1C0_SET_FALCON18

#define P_NVC1C0_SET_FALCON18(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON18(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON18, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON19 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON19(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON19 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON19(val, args...) { \
    struct nv_nvc1c0_SET_FALCON19 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON19(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON19 V_NVC1C0_SET_FALCON19

#define P_NVC1C0_SET_FALCON19(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON19(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON19, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON20 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON20(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON20 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON20(val, args...) { \
    struct nv_nvc1c0_SET_FALCON20 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON20(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON20 V_NVC1C0_SET_FALCON20

#define P_NVC1C0_SET_FALCON20(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON20(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON20, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON21 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON21(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON21 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON21(val, args...) { \
    struct nv_nvc1c0_SET_FALCON21 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON21(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON21 V_NVC1C0_SET_FALCON21

#define P_NVC1C0_SET_FALCON21(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON21(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON21, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON22 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON22(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON22 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON22(val, args...) { \
    struct nv_nvc1c0_SET_FALCON22 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON22(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON22 V_NVC1C0_SET_FALCON22

#define P_NVC1C0_SET_FALCON22(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON22(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON22, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON23 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON23(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON23 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON23(val, args...) { \
    struct nv_nvc1c0_SET_FALCON23 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON23(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON23 V_NVC1C0_SET_FALCON23

#define P_NVC1C0_SET_FALCON23(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON23(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON23, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON24 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON24(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON24 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON24(val, args...) { \
    struct nv_nvc1c0_SET_FALCON24 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON24(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON24 V_NVC1C0_SET_FALCON24

#define P_NVC1C0_SET_FALCON24(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON24(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON24, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON25 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON25(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON25 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON25(val, args...) { \
    struct nv_nvc1c0_SET_FALCON25 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON25(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON25 V_NVC1C0_SET_FALCON25

#define P_NVC1C0_SET_FALCON25(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON25(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON25, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON26 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON26(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON26 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON26(val, args...) { \
    struct nv_nvc1c0_SET_FALCON26 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON26(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON26 V_NVC1C0_SET_FALCON26

#define P_NVC1C0_SET_FALCON26(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON26(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON26, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON27 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON27(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON27 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON27(val, args...) { \
    struct nv_nvc1c0_SET_FALCON27 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON27(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON27 V_NVC1C0_SET_FALCON27

#define P_NVC1C0_SET_FALCON27(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON27(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON27, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON28 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON28(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON28 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON28(val, args...) { \
    struct nv_nvc1c0_SET_FALCON28 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON28(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON28 V_NVC1C0_SET_FALCON28

#define P_NVC1C0_SET_FALCON28(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON28(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON28, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON29 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON29(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON29 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON29(val, args...) { \
    struct nv_nvc1c0_SET_FALCON29 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON29(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON29 V_NVC1C0_SET_FALCON29

#define P_NVC1C0_SET_FALCON29(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON29(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON29, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON30 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON30(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON30 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON30(val, args...) { \
    struct nv_nvc1c0_SET_FALCON30 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON30(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON30 V_NVC1C0_SET_FALCON30

#define P_NVC1C0_SET_FALCON30(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON30(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON30, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_FALCON31 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_FALCON31(uint32_t *val_out, struct nv_nvc1c0_SET_FALCON31 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_FALCON31(val, args...) { \
    struct nv_nvc1c0_SET_FALCON31 __data = { .v = (args) }; \
    __NVC1C0_SET_FALCON31(&val, __data); \
}

#define VA_NVC1C0_SET_FALCON31 V_NVC1C0_SET_FALCON31

#define P_NVC1C0_SET_FALCON31(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_FALCON31(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_FALCON31, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_WINDOW {
    uint32_t base_address;
};

static inline void
__NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_WINDOW st)
{
    uint32_t val = 0;
    
    val |= st.base_address;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_WINDOW __data = { .base_address = (args) }; \
    __NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW V_NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW

#define P_NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_A {
    uint32_t address_upper;
};

static inline void
__NVC1C0_SET_SHADER_LOCAL_MEMORY_A(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_A st)
{
    uint32_t val = 0;
    
    assert(st.address_upper < (UINT64_C(1) << 17));
    val |= st.address_upper << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_LOCAL_MEMORY_A(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_A __data = { .address_upper = (args) }; \
    __NVC1C0_SET_SHADER_LOCAL_MEMORY_A(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_LOCAL_MEMORY_A V_NVC1C0_SET_SHADER_LOCAL_MEMORY_A

#define P_NVC1C0_SET_SHADER_LOCAL_MEMORY_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_LOCAL_MEMORY_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_LOCAL_MEMORY_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_B {
    uint32_t address_lower;
};

static inline void
__NVC1C0_SET_SHADER_LOCAL_MEMORY_B(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_B st)
{
    uint32_t val = 0;
    
    val |= st.address_lower;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_LOCAL_MEMORY_B(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_B __data = { .address_lower = (args) }; \
    __NVC1C0_SET_SHADER_LOCAL_MEMORY_B(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_LOCAL_MEMORY_B V_NVC1C0_SET_SHADER_LOCAL_MEMORY_B

#define P_NVC1C0_SET_SHADER_LOCAL_MEMORY_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_LOCAL_MEMORY_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_LOCAL_MEMORY_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_WINDOW_A {
    uint32_t base_address_upper;
};

static inline void
__NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_WINDOW_A st)
{
    uint32_t val = 0;
    
    assert(st.base_address_upper < (UINT64_C(1) << 17));
    val |= st.base_address_upper << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_WINDOW_A __data = { .base_address_upper = (args) }; \
    __NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A V_NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A

#define P_NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_WINDOW_B {
    uint32_t base_address;
};

static inline void
__NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_WINDOW_B st)
{
    uint32_t val = 0;
    
    val |= st.base_address;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_LOCAL_MEMORY_WINDOW_B __data = { .base_address = (args) }; \
    __NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B V_NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B

#define P_NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_CACHE_CONTROL {
    uint32_t icache_prefetch_enable;
};

static inline void
__NVC1C0_SET_SHADER_CACHE_CONTROL(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_CACHE_CONTROL st)
{
    uint32_t val = 0;
    
    assert(st.icache_prefetch_enable < (UINT64_C(1) << 1));
    val |= st.icache_prefetch_enable << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_CACHE_CONTROL(val, args...) { \
    UNUSED uint32_t ICACHE_PREFETCH_ENABLE_FALSE = NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE; \
    UNUSED uint32_t ICACHE_PREFETCH_ENABLE_TRUE = NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE; \
    struct nv_nvc1c0_SET_SHADER_CACHE_CONTROL __data = { .icache_prefetch_enable = (args) }; \
    __NVC1C0_SET_SHADER_CACHE_CONTROL(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_CACHE_CONTROL V_NVC1C0_SET_SHADER_CACHE_CONTROL

#define P_NVC1C0_SET_SHADER_CACHE_CONTROL(push, args...) do { \
    UNUSED uint32_t ICACHE_PREFETCH_ENABLE_FALSE = NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE; \
    UNUSED uint32_t ICACHE_PREFETCH_ENABLE_TRUE = NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_CACHE_CONTROL(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_CACHE_CONTROL, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SM_TIMEOUT_INTERVAL {
    uint32_t counter_bit;
};

static inline void
__NVC1C0_SET_SM_TIMEOUT_INTERVAL(uint32_t *val_out, struct nv_nvc1c0_SET_SM_TIMEOUT_INTERVAL st)
{
    uint32_t val = 0;
    
    assert(st.counter_bit < (UINT64_C(1) << 6));
    val |= st.counter_bit << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_SM_TIMEOUT_INTERVAL(val, args...) { \
    struct nv_nvc1c0_SET_SM_TIMEOUT_INTERVAL __data = { .counter_bit = (args) }; \
    __NVC1C0_SET_SM_TIMEOUT_INTERVAL(&val, __data); \
}

#define VA_NVC1C0_SET_SM_TIMEOUT_INTERVAL V_NVC1C0_SET_SM_TIMEOUT_INTERVAL

#define P_NVC1C0_SET_SM_TIMEOUT_INTERVAL(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SM_TIMEOUT_INTERVAL(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SM_TIMEOUT_INTERVAL, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP12 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP12(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP12 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP12(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP12 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP12(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP12 V_NVC1C0_SET_SPARE_NOOP12

#define P_NVC1C0_SET_SPARE_NOOP12(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP12(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP12, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP13 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP13(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP13 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP13(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP13 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP13(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP13 V_NVC1C0_SET_SPARE_NOOP13

#define P_NVC1C0_SET_SPARE_NOOP13(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP13(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP13, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP14 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP14(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP14 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP14(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP14 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP14(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP14 V_NVC1C0_SET_SPARE_NOOP14

#define P_NVC1C0_SET_SPARE_NOOP14(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP14(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP14, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP15 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP15(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP15 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP15(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP15 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP15(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP15 V_NVC1C0_SET_SPARE_NOOP15

#define P_NVC1C0_SET_SPARE_NOOP15(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP15(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP15, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP00 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP00(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP00 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP00(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP00 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP00(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP00 V_NVC1C0_SET_SPARE_NOOP00

#define P_NVC1C0_SET_SPARE_NOOP00(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP00(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP00, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP01 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP01(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP01 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP01(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP01 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP01(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP01 V_NVC1C0_SET_SPARE_NOOP01

#define P_NVC1C0_SET_SPARE_NOOP01(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP01(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP01, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP02 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP02(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP02 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP02(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP02 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP02(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP02 V_NVC1C0_SET_SPARE_NOOP02

#define P_NVC1C0_SET_SPARE_NOOP02(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP02(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP02, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP03 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP03(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP03 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP03(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP03 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP03(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP03 V_NVC1C0_SET_SPARE_NOOP03

#define P_NVC1C0_SET_SPARE_NOOP03(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP03(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP03, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP04 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP04(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP04 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP04(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP04 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP04(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP04 V_NVC1C0_SET_SPARE_NOOP04

#define P_NVC1C0_SET_SPARE_NOOP04(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP04(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP04, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP05 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP05(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP05 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP05(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP05 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP05(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP05 V_NVC1C0_SET_SPARE_NOOP05

#define P_NVC1C0_SET_SPARE_NOOP05(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP05(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP05, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP06 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP06(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP06 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP06(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP06 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP06(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP06 V_NVC1C0_SET_SPARE_NOOP06

#define P_NVC1C0_SET_SPARE_NOOP06(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP06(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP06, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP07 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP07(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP07 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP07(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP07 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP07(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP07 V_NVC1C0_SET_SPARE_NOOP07

#define P_NVC1C0_SET_SPARE_NOOP07(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP07(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP07, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP08 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP08(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP08 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP08(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP08 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP08(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP08 V_NVC1C0_SET_SPARE_NOOP08

#define P_NVC1C0_SET_SPARE_NOOP08(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP08(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP08, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP09 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP09(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP09 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP09(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP09 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP09(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP09 V_NVC1C0_SET_SPARE_NOOP09

#define P_NVC1C0_SET_SPARE_NOOP09(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP09(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP09, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP10 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP10(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP10 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP10(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP10 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP10(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP10 V_NVC1C0_SET_SPARE_NOOP10

#define P_NVC1C0_SET_SPARE_NOOP10(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP10(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP10, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE_NOOP11 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE_NOOP11(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE_NOOP11 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE_NOOP11(val, args...) { \
    struct nv_nvc1c0_SET_SPARE_NOOP11 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE_NOOP11(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE_NOOP11 V_NVC1C0_SET_SPARE_NOOP11

#define P_NVC1C0_SET_SPARE_NOOP11(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE_NOOP11(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE_NOOP11, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_INVALIDATE_SAMPLER_CACHE_ALL {
    uint32_t v;
};

static inline void
__NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL(uint32_t *val_out, struct nv_nvc1c0_INVALIDATE_SAMPLER_CACHE_ALL st)
{
    uint32_t val = 0;
    
    assert(st.v < (UINT64_C(1) << 1));
    val |= st.v << 0;
    *val_out = val;
}

#define V_NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL(val, args...) { \
    struct nv_nvc1c0_INVALIDATE_SAMPLER_CACHE_ALL __data = { .v = (args) }; \
    __NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL(&val, __data); \
}

#define VA_NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL V_NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL

#define P_NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL {
    uint32_t v;
};

static inline void
__NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL(uint32_t *val_out, struct nv_nvc1c0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL st)
{
    uint32_t val = 0;
    
    assert(st.v < (UINT64_C(1) << 1));
    val |= st.v << 0;
    *val_out = val;
}

#define V_NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL(val, args...) { \
    struct nv_nvc1c0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL __data = { .v = (args) }; \
    __NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL(&val, __data); \
}

#define VA_NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL V_NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL

#define P_NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI {
    uint32_t lines;
    uint32_t tag;
};

static inline void
__NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI(uint32_t *val_out, struct nv_nvc1c0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI st)
{
    uint32_t val = 0;
    
    assert(st.lines < (UINT64_C(1) << 1));
    val |= st.lines << 0;
    
    assert(st.tag < (UINT64_C(1) << 22));
    val |= st.tag << 4;
    *val_out = val;
}

#define V_NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI(val, args...) { \
    UNUSED uint32_t LINES_ALL = NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL; \
    UNUSED uint32_t LINES_ONE = NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE; \
    struct nv_nvc1c0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI __data = args; \
    __NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI(&val, __data); \
}

#define VA_NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI V_NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI

#define P_NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI(push, args...) do { \
    UNUSED uint32_t LINES_ALL = NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL; \
    UNUSED uint32_t LINES_ONE = NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT {
    uint32_t all;
};

static inline void
__NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT(uint32_t *val_out, struct nv_nvc1c0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT st)
{
    uint32_t val = 0;
    
    assert(st.all < (UINT64_C(1) << 1));
    val |= st.all << 0;
    *val_out = val;
}

#define V_NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT(val, args...) { \
    UNUSED uint32_t ALL_FALSE = NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE; \
    UNUSED uint32_t ALL_TRUE = NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE; \
    struct nv_nvc1c0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT __data = { .all = (args) }; \
    __NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT(&val, __data); \
}

#define VA_NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT V_NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT

#define P_NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT(push, args...) do { \
    UNUSED uint32_t ALL_FALSE = NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE; \
    UNUSED uint32_t ALL_TRUE = NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_INVALIDATE_SAMPLER_CACHE {
    uint32_t lines;
    uint32_t tag;
};

static inline void
__NVC1C0_INVALIDATE_SAMPLER_CACHE(uint32_t *val_out, struct nv_nvc1c0_INVALIDATE_SAMPLER_CACHE st)
{
    uint32_t val = 0;
    
    assert(st.lines < (UINT64_C(1) << 1));
    val |= st.lines << 0;
    
    assert(st.tag < (UINT64_C(1) << 22));
    val |= st.tag << 4;
    *val_out = val;
}

#define V_NVC1C0_INVALIDATE_SAMPLER_CACHE(val, args...) { \
    UNUSED uint32_t LINES_ALL = NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL; \
    UNUSED uint32_t LINES_ONE = NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE; \
    struct nv_nvc1c0_INVALIDATE_SAMPLER_CACHE __data = args; \
    __NVC1C0_INVALIDATE_SAMPLER_CACHE(&val, __data); \
}

#define VA_NVC1C0_INVALIDATE_SAMPLER_CACHE V_NVC1C0_INVALIDATE_SAMPLER_CACHE

#define P_NVC1C0_INVALIDATE_SAMPLER_CACHE(push, args...) do { \
    UNUSED uint32_t LINES_ALL = NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL; \
    UNUSED uint32_t LINES_ONE = NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_INVALIDATE_SAMPLER_CACHE(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_INVALIDATE_SAMPLER_CACHE, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_INVALIDATE_TEXTURE_HEADER_CACHE {
    uint32_t lines;
    uint32_t tag;
};

static inline void
__NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE(uint32_t *val_out, struct nv_nvc1c0_INVALIDATE_TEXTURE_HEADER_CACHE st)
{
    uint32_t val = 0;
    
    assert(st.lines < (UINT64_C(1) << 1));
    val |= st.lines << 0;
    
    assert(st.tag < (UINT64_C(1) << 22));
    val |= st.tag << 4;
    *val_out = val;
}

#define V_NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE(val, args...) { \
    UNUSED uint32_t LINES_ALL = NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL; \
    UNUSED uint32_t LINES_ONE = NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE; \
    struct nv_nvc1c0_INVALIDATE_TEXTURE_HEADER_CACHE __data = args; \
    __NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE(&val, __data); \
}

#define VA_NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE V_NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE

#define P_NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE(push, args...) do { \
    UNUSED uint32_t LINES_ALL = NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL; \
    UNUSED uint32_t LINES_ONE = NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_INVALIDATE_TEXTURE_DATA_CACHE {
    uint32_t lines;
    uint32_t tag;
};

static inline void
__NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE(uint32_t *val_out, struct nv_nvc1c0_INVALIDATE_TEXTURE_DATA_CACHE st)
{
    uint32_t val = 0;
    
    assert(st.lines < (UINT64_C(1) << 1));
    val |= st.lines << 0;
    
    assert(st.tag < (UINT64_C(1) << 22));
    val |= st.tag << 4;
    *val_out = val;
}

#define V_NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE(val, args...) { \
    UNUSED uint32_t LINES_ALL = NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL; \
    UNUSED uint32_t LINES_ONE = NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE; \
    struct nv_nvc1c0_INVALIDATE_TEXTURE_DATA_CACHE __data = args; \
    __NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE(&val, __data); \
}

#define VA_NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE V_NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE

#define P_NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE(push, args...) do { \
    UNUSED uint32_t LINES_ALL = NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL; \
    UNUSED uint32_t LINES_ONE = NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_INVALIDATE_SAMPLER_CACHE_NO_WFI {
    uint32_t lines;
    uint32_t tag;
};

static inline void
__NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI(uint32_t *val_out, struct nv_nvc1c0_INVALIDATE_SAMPLER_CACHE_NO_WFI st)
{
    uint32_t val = 0;
    
    assert(st.lines < (UINT64_C(1) << 1));
    val |= st.lines << 0;
    
    assert(st.tag < (UINT64_C(1) << 22));
    val |= st.tag << 4;
    *val_out = val;
}

#define V_NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI(val, args...) { \
    UNUSED uint32_t LINES_ALL = NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL; \
    UNUSED uint32_t LINES_ONE = NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE; \
    struct nv_nvc1c0_INVALIDATE_SAMPLER_CACHE_NO_WFI __data = args; \
    __NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI(&val, __data); \
}

#define VA_NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI V_NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI

#define P_NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI(push, args...) do { \
    UNUSED uint32_t LINES_ALL = NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL; \
    UNUSED uint32_t LINES_ONE = NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_EXCEPTIONS {
    uint32_t enable;
};

static inline void
__NVC1C0_SET_SHADER_EXCEPTIONS(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_EXCEPTIONS st)
{
    uint32_t val = 0;
    
    assert(st.enable < (UINT64_C(1) << 1));
    val |= st.enable << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_EXCEPTIONS(val, args...) { \
    UNUSED uint32_t ENABLE_FALSE = NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE; \
    UNUSED uint32_t ENABLE_TRUE = NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE; \
    struct nv_nvc1c0_SET_SHADER_EXCEPTIONS __data = { .enable = (args) }; \
    __NVC1C0_SET_SHADER_EXCEPTIONS(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_EXCEPTIONS V_NVC1C0_SET_SHADER_EXCEPTIONS

#define P_NVC1C0_SET_SHADER_EXCEPTIONS(push, args...) do { \
    UNUSED uint32_t ENABLE_FALSE = NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE; \
    UNUSED uint32_t ENABLE_TRUE = NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_EXCEPTIONS(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_EXCEPTIONS, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RENDER_ENABLE_A {
    uint32_t offset_upper;
};

static inline void
__NVC1C0_SET_RENDER_ENABLE_A(uint32_t *val_out, struct nv_nvc1c0_SET_RENDER_ENABLE_A st)
{
    uint32_t val = 0;
    
    assert(st.offset_upper < (UINT64_C(1) << 8));
    val |= st.offset_upper << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_RENDER_ENABLE_A(val, args...) { \
    struct nv_nvc1c0_SET_RENDER_ENABLE_A __data = { .offset_upper = (args) }; \
    __NVC1C0_SET_RENDER_ENABLE_A(&val, __data); \
}

#define VA_NVC1C0_SET_RENDER_ENABLE_A V_NVC1C0_SET_RENDER_ENABLE_A

#define P_NVC1C0_SET_RENDER_ENABLE_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RENDER_ENABLE_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RENDER_ENABLE_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RENDER_ENABLE_B {
    uint32_t offset_lower;
};

static inline void
__NVC1C0_SET_RENDER_ENABLE_B(uint32_t *val_out, struct nv_nvc1c0_SET_RENDER_ENABLE_B st)
{
    uint32_t val = 0;
    
    val |= st.offset_lower;
    *val_out = val;
}

#define V_NVC1C0_SET_RENDER_ENABLE_B(val, args...) { \
    struct nv_nvc1c0_SET_RENDER_ENABLE_B __data = { .offset_lower = (args) }; \
    __NVC1C0_SET_RENDER_ENABLE_B(&val, __data); \
}

#define VA_NVC1C0_SET_RENDER_ENABLE_B V_NVC1C0_SET_RENDER_ENABLE_B

#define P_NVC1C0_SET_RENDER_ENABLE_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RENDER_ENABLE_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RENDER_ENABLE_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RENDER_ENABLE_C {
    uint32_t mode;
};

static inline void
__NVC1C0_SET_RENDER_ENABLE_C(uint32_t *val_out, struct nv_nvc1c0_SET_RENDER_ENABLE_C st)
{
    uint32_t val = 0;
    
    assert(st.mode < (UINT64_C(1) << 3));
    val |= st.mode << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_RENDER_ENABLE_C(val, args...) { \
    UNUSED uint32_t MODE_FALSE = NVC1C0_SET_RENDER_ENABLE_C_MODE_FALSE; \
    UNUSED uint32_t MODE_TRUE = NVC1C0_SET_RENDER_ENABLE_C_MODE_TRUE; \
    UNUSED uint32_t MODE_CONDITIONAL = NVC1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL; \
    UNUSED uint32_t MODE_RENDER_IF_EQUAL = NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL; \
    UNUSED uint32_t MODE_RENDER_IF_NOT_EQUAL = NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL; \
    struct nv_nvc1c0_SET_RENDER_ENABLE_C __data = { .mode = (args) }; \
    __NVC1C0_SET_RENDER_ENABLE_C(&val, __data); \
}

#define VA_NVC1C0_SET_RENDER_ENABLE_C V_NVC1C0_SET_RENDER_ENABLE_C

#define P_NVC1C0_SET_RENDER_ENABLE_C(push, args...) do { \
    UNUSED uint32_t MODE_FALSE = NVC1C0_SET_RENDER_ENABLE_C_MODE_FALSE; \
    UNUSED uint32_t MODE_TRUE = NVC1C0_SET_RENDER_ENABLE_C_MODE_TRUE; \
    UNUSED uint32_t MODE_CONDITIONAL = NVC1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL; \
    UNUSED uint32_t MODE_RENDER_IF_EQUAL = NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL; \
    UNUSED uint32_t MODE_RENDER_IF_NOT_EQUAL = NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RENDER_ENABLE_C(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RENDER_ENABLE_C, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_TEX_SAMPLER_POOL_A {
    uint32_t offset_upper;
};

static inline void
__NVC1C0_SET_TEX_SAMPLER_POOL_A(uint32_t *val_out, struct nv_nvc1c0_SET_TEX_SAMPLER_POOL_A st)
{
    uint32_t val = 0;
    
    assert(st.offset_upper < (UINT64_C(1) << 17));
    val |= st.offset_upper << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_TEX_SAMPLER_POOL_A(val, args...) { \
    struct nv_nvc1c0_SET_TEX_SAMPLER_POOL_A __data = { .offset_upper = (args) }; \
    __NVC1C0_SET_TEX_SAMPLER_POOL_A(&val, __data); \
}

#define VA_NVC1C0_SET_TEX_SAMPLER_POOL_A V_NVC1C0_SET_TEX_SAMPLER_POOL_A

#define P_NVC1C0_SET_TEX_SAMPLER_POOL_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_TEX_SAMPLER_POOL_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_TEX_SAMPLER_POOL_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_TEX_SAMPLER_POOL_B {
    uint32_t offset_lower;
};

static inline void
__NVC1C0_SET_TEX_SAMPLER_POOL_B(uint32_t *val_out, struct nv_nvc1c0_SET_TEX_SAMPLER_POOL_B st)
{
    uint32_t val = 0;
    
    val |= st.offset_lower;
    *val_out = val;
}

#define V_NVC1C0_SET_TEX_SAMPLER_POOL_B(val, args...) { \
    struct nv_nvc1c0_SET_TEX_SAMPLER_POOL_B __data = { .offset_lower = (args) }; \
    __NVC1C0_SET_TEX_SAMPLER_POOL_B(&val, __data); \
}

#define VA_NVC1C0_SET_TEX_SAMPLER_POOL_B V_NVC1C0_SET_TEX_SAMPLER_POOL_B

#define P_NVC1C0_SET_TEX_SAMPLER_POOL_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_TEX_SAMPLER_POOL_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_TEX_SAMPLER_POOL_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_TEX_SAMPLER_POOL_C {
    uint32_t maximum_index;
};

static inline void
__NVC1C0_SET_TEX_SAMPLER_POOL_C(uint32_t *val_out, struct nv_nvc1c0_SET_TEX_SAMPLER_POOL_C st)
{
    uint32_t val = 0;
    
    assert(st.maximum_index < (UINT64_C(1) << 20));
    val |= st.maximum_index << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_TEX_SAMPLER_POOL_C(val, args...) { \
    struct nv_nvc1c0_SET_TEX_SAMPLER_POOL_C __data = { .maximum_index = (args) }; \
    __NVC1C0_SET_TEX_SAMPLER_POOL_C(&val, __data); \
}

#define VA_NVC1C0_SET_TEX_SAMPLER_POOL_C V_NVC1C0_SET_TEX_SAMPLER_POOL_C

#define P_NVC1C0_SET_TEX_SAMPLER_POOL_C(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_TEX_SAMPLER_POOL_C(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_TEX_SAMPLER_POOL_C, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_TEX_HEADER_POOL_A {
    uint32_t offset_upper;
};

static inline void
__NVC1C0_SET_TEX_HEADER_POOL_A(uint32_t *val_out, struct nv_nvc1c0_SET_TEX_HEADER_POOL_A st)
{
    uint32_t val = 0;
    
    assert(st.offset_upper < (UINT64_C(1) << 17));
    val |= st.offset_upper << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_TEX_HEADER_POOL_A(val, args...) { \
    struct nv_nvc1c0_SET_TEX_HEADER_POOL_A __data = { .offset_upper = (args) }; \
    __NVC1C0_SET_TEX_HEADER_POOL_A(&val, __data); \
}

#define VA_NVC1C0_SET_TEX_HEADER_POOL_A V_NVC1C0_SET_TEX_HEADER_POOL_A

#define P_NVC1C0_SET_TEX_HEADER_POOL_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_TEX_HEADER_POOL_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_TEX_HEADER_POOL_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_TEX_HEADER_POOL_B {
    uint32_t offset_lower;
};

static inline void
__NVC1C0_SET_TEX_HEADER_POOL_B(uint32_t *val_out, struct nv_nvc1c0_SET_TEX_HEADER_POOL_B st)
{
    uint32_t val = 0;
    
    val |= st.offset_lower;
    *val_out = val;
}

#define V_NVC1C0_SET_TEX_HEADER_POOL_B(val, args...) { \
    struct nv_nvc1c0_SET_TEX_HEADER_POOL_B __data = { .offset_lower = (args) }; \
    __NVC1C0_SET_TEX_HEADER_POOL_B(&val, __data); \
}

#define VA_NVC1C0_SET_TEX_HEADER_POOL_B V_NVC1C0_SET_TEX_HEADER_POOL_B

#define P_NVC1C0_SET_TEX_HEADER_POOL_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_TEX_HEADER_POOL_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_TEX_HEADER_POOL_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_TEX_HEADER_POOL_C {
    uint32_t maximum_index;
};

static inline void
__NVC1C0_SET_TEX_HEADER_POOL_C(uint32_t *val_out, struct nv_nvc1c0_SET_TEX_HEADER_POOL_C st)
{
    uint32_t val = 0;
    
    assert(st.maximum_index < (UINT64_C(1) << 22));
    val |= st.maximum_index << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_TEX_HEADER_POOL_C(val, args...) { \
    struct nv_nvc1c0_SET_TEX_HEADER_POOL_C __data = { .maximum_index = (args) }; \
    __NVC1C0_SET_TEX_HEADER_POOL_C(&val, __data); \
}

#define VA_NVC1C0_SET_TEX_HEADER_POOL_C V_NVC1C0_SET_TEX_HEADER_POOL_C

#define P_NVC1C0_SET_TEX_HEADER_POOL_C(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_TEX_HEADER_POOL_C(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_TEX_HEADER_POOL_C, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_PROGRAM_REGION_A {
    uint32_t address_upper;
};

static inline void
__NVC1C0_SET_PROGRAM_REGION_A(uint32_t *val_out, struct nv_nvc1c0_SET_PROGRAM_REGION_A st)
{
    uint32_t val = 0;
    
    assert(st.address_upper < (UINT64_C(1) << 17));
    val |= st.address_upper << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_PROGRAM_REGION_A(val, args...) { \
    struct nv_nvc1c0_SET_PROGRAM_REGION_A __data = { .address_upper = (args) }; \
    __NVC1C0_SET_PROGRAM_REGION_A(&val, __data); \
}

#define VA_NVC1C0_SET_PROGRAM_REGION_A V_NVC1C0_SET_PROGRAM_REGION_A

#define P_NVC1C0_SET_PROGRAM_REGION_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_PROGRAM_REGION_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_PROGRAM_REGION_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_PROGRAM_REGION_B {
    uint32_t address_lower;
};

static inline void
__NVC1C0_SET_PROGRAM_REGION_B(uint32_t *val_out, struct nv_nvc1c0_SET_PROGRAM_REGION_B st)
{
    uint32_t val = 0;
    
    val |= st.address_lower;
    *val_out = val;
}

#define V_NVC1C0_SET_PROGRAM_REGION_B(val, args...) { \
    struct nv_nvc1c0_SET_PROGRAM_REGION_B __data = { .address_lower = (args) }; \
    __NVC1C0_SET_PROGRAM_REGION_B(&val, __data); \
}

#define VA_NVC1C0_SET_PROGRAM_REGION_B V_NVC1C0_SET_PROGRAM_REGION_B

#define P_NVC1C0_SET_PROGRAM_REGION_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_PROGRAM_REGION_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_PROGRAM_REGION_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_INVALIDATE_SHADER_CACHES_NO_WFI {
    uint32_t instruction;
    uint32_t global_data;
    uint32_t constant;
};

static inline void
__NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI(uint32_t *val_out, struct nv_nvc1c0_INVALIDATE_SHADER_CACHES_NO_WFI st)
{
    uint32_t val = 0;
    
    assert(st.instruction < (UINT64_C(1) << 1));
    val |= st.instruction << 0;
    
    assert(st.global_data < (UINT64_C(1) << 1));
    val |= st.global_data << 4;
    
    assert(st.constant < (UINT64_C(1) << 1));
    val |= st.constant << 12;
    *val_out = val;
}

#define V_NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI(val, args...) { \
    UNUSED uint32_t INSTRUCTION_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE; \
    UNUSED uint32_t INSTRUCTION_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE; \
    UNUSED uint32_t GLOBAL_DATA_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE; \
    UNUSED uint32_t GLOBAL_DATA_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE; \
    UNUSED uint32_t CONSTANT_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE; \
    UNUSED uint32_t CONSTANT_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE; \
    struct nv_nvc1c0_INVALIDATE_SHADER_CACHES_NO_WFI __data = args; \
    __NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI(&val, __data); \
}

#define VA_NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI V_NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI

#define P_NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI(push, args...) do { \
    UNUSED uint32_t INSTRUCTION_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE; \
    UNUSED uint32_t INSTRUCTION_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE; \
    UNUSED uint32_t GLOBAL_DATA_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE; \
    UNUSED uint32_t GLOBAL_DATA_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE; \
    UNUSED uint32_t CONSTANT_FALSE = NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE; \
    UNUSED uint32_t CONSTANT_TRUE = NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_RENDER_ENABLE_OVERRIDE {
    uint32_t mode;
};

static inline void
__NVC1C0_SET_RENDER_ENABLE_OVERRIDE(uint32_t *val_out, struct nv_nvc1c0_SET_RENDER_ENABLE_OVERRIDE st)
{
    uint32_t val = 0;
    
    assert(st.mode < (UINT64_C(1) << 2));
    val |= st.mode << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_RENDER_ENABLE_OVERRIDE(val, args...) { \
    UNUSED uint32_t MODE_USE_RENDER_ENABLE = NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE; \
    UNUSED uint32_t MODE_ALWAYS_RENDER = NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER; \
    UNUSED uint32_t MODE_NEVER_RENDER = NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER; \
    struct nv_nvc1c0_SET_RENDER_ENABLE_OVERRIDE __data = { .mode = (args) }; \
    __NVC1C0_SET_RENDER_ENABLE_OVERRIDE(&val, __data); \
}

#define VA_NVC1C0_SET_RENDER_ENABLE_OVERRIDE V_NVC1C0_SET_RENDER_ENABLE_OVERRIDE

#define P_NVC1C0_SET_RENDER_ENABLE_OVERRIDE(push, args...) do { \
    UNUSED uint32_t MODE_USE_RENDER_ENABLE = NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE; \
    UNUSED uint32_t MODE_ALWAYS_RENDER = NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER; \
    UNUSED uint32_t MODE_NEVER_RENDER = NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_RENDER_ENABLE_OVERRIDE(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_RENDER_ENABLE_OVERRIDE, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_PIPE_NOP {
    uint32_t v;
};

static inline void
__NVC1C0_PIPE_NOP(uint32_t *val_out, struct nv_nvc1c0_PIPE_NOP st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_PIPE_NOP(val, args...) { \
    struct nv_nvc1c0_PIPE_NOP __data = { .v = (args) }; \
    __NVC1C0_PIPE_NOP(&val, __data); \
}

#define VA_NVC1C0_PIPE_NOP V_NVC1C0_PIPE_NOP

#define P_NVC1C0_PIPE_NOP(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_PIPE_NOP(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_PIPE_NOP, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE00 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE00(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE00 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE00(val, args...) { \
    struct nv_nvc1c0_SET_SPARE00 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE00(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE00 V_NVC1C0_SET_SPARE00

#define P_NVC1C0_SET_SPARE00(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE00(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE00, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE01 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE01(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE01 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE01(val, args...) { \
    struct nv_nvc1c0_SET_SPARE01 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE01(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE01 V_NVC1C0_SET_SPARE01

#define P_NVC1C0_SET_SPARE01(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE01(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE01, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE02 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE02(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE02 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE02(val, args...) { \
    struct nv_nvc1c0_SET_SPARE02 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE02(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE02 V_NVC1C0_SET_SPARE02

#define P_NVC1C0_SET_SPARE02(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE02(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE02, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SPARE03 {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SPARE03(uint32_t *val_out, struct nv_nvc1c0_SET_SPARE03 st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SPARE03(val, args...) { \
    struct nv_nvc1c0_SET_SPARE03 __data = { .v = (args) }; \
    __NVC1C0_SET_SPARE03(&val, __data); \
}

#define VA_NVC1C0_SET_SPARE03 V_NVC1C0_SET_SPARE03

#define P_NVC1C0_SET_SPARE03(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SPARE03(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SPARE03, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_REPORT_SEMAPHORE_A {
    uint32_t offset_upper;
};

static inline void
__NVC1C0_SET_REPORT_SEMAPHORE_A(uint32_t *val_out, struct nv_nvc1c0_SET_REPORT_SEMAPHORE_A st)
{
    uint32_t val = 0;
    
    assert(st.offset_upper < (UINT64_C(1) << 8));
    val |= st.offset_upper << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_REPORT_SEMAPHORE_A(val, args...) { \
    struct nv_nvc1c0_SET_REPORT_SEMAPHORE_A __data = { .offset_upper = (args) }; \
    __NVC1C0_SET_REPORT_SEMAPHORE_A(&val, __data); \
}

#define VA_NVC1C0_SET_REPORT_SEMAPHORE_A V_NVC1C0_SET_REPORT_SEMAPHORE_A

#define P_NVC1C0_SET_REPORT_SEMAPHORE_A(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_REPORT_SEMAPHORE_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_REPORT_SEMAPHORE_A, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_REPORT_SEMAPHORE_B {
    uint32_t offset_lower;
};

static inline void
__NVC1C0_SET_REPORT_SEMAPHORE_B(uint32_t *val_out, struct nv_nvc1c0_SET_REPORT_SEMAPHORE_B st)
{
    uint32_t val = 0;
    
    val |= st.offset_lower;
    *val_out = val;
}

#define V_NVC1C0_SET_REPORT_SEMAPHORE_B(val, args...) { \
    struct nv_nvc1c0_SET_REPORT_SEMAPHORE_B __data = { .offset_lower = (args) }; \
    __NVC1C0_SET_REPORT_SEMAPHORE_B(&val, __data); \
}

#define VA_NVC1C0_SET_REPORT_SEMAPHORE_B V_NVC1C0_SET_REPORT_SEMAPHORE_B

#define P_NVC1C0_SET_REPORT_SEMAPHORE_B(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_REPORT_SEMAPHORE_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_REPORT_SEMAPHORE_B, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_REPORT_SEMAPHORE_C {
    uint32_t payload;
};

static inline void
__NVC1C0_SET_REPORT_SEMAPHORE_C(uint32_t *val_out, struct nv_nvc1c0_SET_REPORT_SEMAPHORE_C st)
{
    uint32_t val = 0;
    
    val |= st.payload;
    *val_out = val;
}

#define V_NVC1C0_SET_REPORT_SEMAPHORE_C(val, args...) { \
    struct nv_nvc1c0_SET_REPORT_SEMAPHORE_C __data = { .payload = (args) }; \
    __NVC1C0_SET_REPORT_SEMAPHORE_C(&val, __data); \
}

#define VA_NVC1C0_SET_REPORT_SEMAPHORE_C V_NVC1C0_SET_REPORT_SEMAPHORE_C

#define P_NVC1C0_SET_REPORT_SEMAPHORE_C(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_REPORT_SEMAPHORE_C(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_REPORT_SEMAPHORE_C, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_REPORT_SEMAPHORE_D {
    uint32_t operation;
    uint32_t awaken_enable;
    uint32_t structure_size;
    uint32_t flush_disable;
    uint32_t reduction_enable;
    uint32_t reduction_op;
    uint32_t reduction_format;
};

static inline void
__NVC1C0_SET_REPORT_SEMAPHORE_D(uint32_t *val_out, struct nv_nvc1c0_SET_REPORT_SEMAPHORE_D st)
{
    uint32_t val = 0;
    
    assert(st.operation < (UINT64_C(1) << 2));
    val |= st.operation << 0;
    
    assert(st.awaken_enable < (UINT64_C(1) << 1));
    val |= st.awaken_enable << 20;
    
    assert(st.structure_size < (UINT64_C(1) << 1));
    val |= st.structure_size << 28;
    
    assert(st.flush_disable < (UINT64_C(1) << 1));
    val |= st.flush_disable << 2;
    
    assert(st.reduction_enable < (UINT64_C(1) << 1));
    val |= st.reduction_enable << 3;
    
    assert(st.reduction_op < (UINT64_C(1) << 3));
    val |= st.reduction_op << 9;
    
    assert(st.reduction_format < (UINT64_C(1) << 2));
    val |= st.reduction_format << 17;
    *val_out = val;
}

#define V_NVC1C0_SET_REPORT_SEMAPHORE_D(val, args...) { \
    UNUSED uint32_t OPERATION_RELEASE = NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE; \
    UNUSED uint32_t OPERATION_TRAP = NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP; \
    UNUSED uint32_t AWAKEN_ENABLE_FALSE = NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE; \
    UNUSED uint32_t AWAKEN_ENABLE_TRUE = NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE; \
    UNUSED uint32_t STRUCTURE_SIZE_FOUR_WORDS = NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS; \
    UNUSED uint32_t STRUCTURE_SIZE_ONE_WORD = NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD; \
    UNUSED uint32_t FLUSH_DISABLE_FALSE = NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE; \
    UNUSED uint32_t FLUSH_DISABLE_TRUE = NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE; \
    UNUSED uint32_t REDUCTION_ENABLE_FALSE = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE; \
    UNUSED uint32_t REDUCTION_ENABLE_TRUE = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE; \
    UNUSED uint32_t REDUCTION_OP_RED_ADD = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD; \
    UNUSED uint32_t REDUCTION_OP_RED_MIN = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN; \
    UNUSED uint32_t REDUCTION_OP_RED_MAX = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX; \
    UNUSED uint32_t REDUCTION_OP_RED_INC = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC; \
    UNUSED uint32_t REDUCTION_OP_RED_DEC = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC; \
    UNUSED uint32_t REDUCTION_OP_RED_AND = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND; \
    UNUSED uint32_t REDUCTION_OP_RED_OR = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR; \
    UNUSED uint32_t REDUCTION_OP_RED_XOR = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR; \
    UNUSED uint32_t REDUCTION_FORMAT_UNSIGNED_32 = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32; \
    UNUSED uint32_t REDUCTION_FORMAT_SIGNED_32 = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32; \
    struct nv_nvc1c0_SET_REPORT_SEMAPHORE_D __data = args; \
    __NVC1C0_SET_REPORT_SEMAPHORE_D(&val, __data); \
}

#define VA_NVC1C0_SET_REPORT_SEMAPHORE_D V_NVC1C0_SET_REPORT_SEMAPHORE_D

#define P_NVC1C0_SET_REPORT_SEMAPHORE_D(push, args...) do { \
    UNUSED uint32_t OPERATION_RELEASE = NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE; \
    UNUSED uint32_t OPERATION_TRAP = NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP; \
    UNUSED uint32_t AWAKEN_ENABLE_FALSE = NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE; \
    UNUSED uint32_t AWAKEN_ENABLE_TRUE = NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE; \
    UNUSED uint32_t STRUCTURE_SIZE_FOUR_WORDS = NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS; \
    UNUSED uint32_t STRUCTURE_SIZE_ONE_WORD = NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD; \
    UNUSED uint32_t FLUSH_DISABLE_FALSE = NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE; \
    UNUSED uint32_t FLUSH_DISABLE_TRUE = NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE; \
    UNUSED uint32_t REDUCTION_ENABLE_FALSE = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE; \
    UNUSED uint32_t REDUCTION_ENABLE_TRUE = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE; \
    UNUSED uint32_t REDUCTION_OP_RED_ADD = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD; \
    UNUSED uint32_t REDUCTION_OP_RED_MIN = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN; \
    UNUSED uint32_t REDUCTION_OP_RED_MAX = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX; \
    UNUSED uint32_t REDUCTION_OP_RED_INC = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC; \
    UNUSED uint32_t REDUCTION_OP_RED_DEC = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC; \
    UNUSED uint32_t REDUCTION_OP_RED_AND = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND; \
    UNUSED uint32_t REDUCTION_OP_RED_OR = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR; \
    UNUSED uint32_t REDUCTION_OP_RED_XOR = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR; \
    UNUSED uint32_t REDUCTION_FORMAT_UNSIGNED_32 = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32; \
    UNUSED uint32_t REDUCTION_FORMAT_SIGNED_32 = NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32; \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_REPORT_SEMAPHORE_D(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_REPORT_SEMAPHORE_D, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_BINDLESS_TEXTURE {
    uint32_t constant_buffer_slot_select;
};

static inline void
__NVC1C0_SET_BINDLESS_TEXTURE(uint32_t *val_out, struct nv_nvc1c0_SET_BINDLESS_TEXTURE st)
{
    uint32_t val = 0;
    
    assert(st.constant_buffer_slot_select < (UINT64_C(1) << 3));
    val |= st.constant_buffer_slot_select << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_BINDLESS_TEXTURE(val, args...) { \
    struct nv_nvc1c0_SET_BINDLESS_TEXTURE __data = { .constant_buffer_slot_select = (args) }; \
    __NVC1C0_SET_BINDLESS_TEXTURE(&val, __data); \
}

#define VA_NVC1C0_SET_BINDLESS_TEXTURE V_NVC1C0_SET_BINDLESS_TEXTURE

#define P_NVC1C0_SET_BINDLESS_TEXTURE(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_BINDLESS_TEXTURE(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_BINDLESS_TEXTURE, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_TRAP_HANDLER {
    uint32_t offset;
};

static inline void
__NVC1C0_SET_TRAP_HANDLER(uint32_t *val_out, struct nv_nvc1c0_SET_TRAP_HANDLER st)
{
    uint32_t val = 0;
    
    val |= st.offset;
    *val_out = val;
}

#define V_NVC1C0_SET_TRAP_HANDLER(val, args...) { \
    struct nv_nvc1c0_SET_TRAP_HANDLER __data = { .offset = (args) }; \
    __NVC1C0_SET_TRAP_HANDLER(&val, __data); \
}

#define VA_NVC1C0_SET_TRAP_HANDLER V_NVC1C0_SET_TRAP_HANDLER

#define P_NVC1C0_SET_TRAP_HANDLER(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_TRAP_HANDLER(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_TRAP_HANDLER, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER __data = { .v = (args) }; \
    __NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER

#define P_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(push, idx, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(idx), nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_VALUE {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_VALUE st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_VALUE __data = { .v = (args) }; \
    __NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE

#define P_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(push, idx, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(idx), nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_EVENT {
    uint32_t event;
};

static inline void
__NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_EVENT st)
{
    uint32_t val = 0;
    
    assert(st.event < (UINT64_C(1) << 8));
    val |= st.event << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_EVENT __data = { .event = (args) }; \
    __NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT

#define P_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(push, idx, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(idx), nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A {
    uint32_t event0;
    uint32_t bit_select0;
    uint32_t event1;
    uint32_t bit_select1;
    uint32_t event2;
    uint32_t bit_select2;
    uint32_t event3;
    uint32_t bit_select3;
    uint32_t event4;
    uint32_t bit_select4;
    uint32_t event5;
    uint32_t bit_select5;
    uint32_t spare;
};

static inline void
__NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A st)
{
    uint32_t val = 0;
    
    assert(st.event0 < (UINT64_C(1) << 2));
    val |= st.event0 << 0;
    
    assert(st.bit_select0 < (UINT64_C(1) << 3));
    val |= st.bit_select0 << 2;
    
    assert(st.event1 < (UINT64_C(1) << 2));
    val |= st.event1 << 5;
    
    assert(st.bit_select1 < (UINT64_C(1) << 3));
    val |= st.bit_select1 << 7;
    
    assert(st.event2 < (UINT64_C(1) << 2));
    val |= st.event2 << 10;
    
    assert(st.bit_select2 < (UINT64_C(1) << 3));
    val |= st.bit_select2 << 12;
    
    assert(st.event3 < (UINT64_C(1) << 2));
    val |= st.event3 << 15;
    
    assert(st.bit_select3 < (UINT64_C(1) << 3));
    val |= st.bit_select3 << 17;
    
    assert(st.event4 < (UINT64_C(1) << 2));
    val |= st.event4 << 20;
    
    assert(st.bit_select4 < (UINT64_C(1) << 3));
    val |= st.bit_select4 << 22;
    
    assert(st.event5 < (UINT64_C(1) << 2));
    val |= st.event5 << 25;
    
    assert(st.bit_select5 < (UINT64_C(1) << 3));
    val |= st.bit_select5 << 27;
    
    assert(st.spare < (UINT64_C(1) << 2));
    val |= st.spare << 30;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A __data = args; \
    __NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A

#define P_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(push, idx, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(idx), nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B {
    uint32_t edge;
    uint32_t mode;
    uint32_t windowed;
    uint32_t func;
};

static inline void
__NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B st)
{
    uint32_t val = 0;
    
    assert(st.edge < (UINT64_C(1) << 1));
    val |= st.edge << 0;
    
    assert(st.mode < (UINT64_C(1) << 2));
    val |= st.mode << 1;
    
    assert(st.windowed < (UINT64_C(1) << 1));
    val |= st.windowed << 3;
    
    assert(st.func < (UINT64_C(1) << 16));
    val |= st.func << 4;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B __data = args; \
    __NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B

#define P_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(push, idx, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(idx), nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL {
    uint32_t mask;
};

static inline void
__NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL st)
{
    uint32_t val = 0;
    
    assert(st.mask < (UINT64_C(1) << 8));
    val |= st.mask << 0;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL __data = { .mask = (args) }; \
    __NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL

#define P_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_START_SHADER_PERFORMANCE_COUNTER {
    uint32_t counter_mask;
};

static inline void
__NVC1C0_START_SHADER_PERFORMANCE_COUNTER(uint32_t *val_out, struct nv_nvc1c0_START_SHADER_PERFORMANCE_COUNTER st)
{
    uint32_t val = 0;
    
    assert(st.counter_mask < (UINT64_C(1) << 8));
    val |= st.counter_mask << 0;
    *val_out = val;
}

#define V_NVC1C0_START_SHADER_PERFORMANCE_COUNTER(val, args...) { \
    struct nv_nvc1c0_START_SHADER_PERFORMANCE_COUNTER __data = { .counter_mask = (args) }; \
    __NVC1C0_START_SHADER_PERFORMANCE_COUNTER(&val, __data); \
}

#define VA_NVC1C0_START_SHADER_PERFORMANCE_COUNTER V_NVC1C0_START_SHADER_PERFORMANCE_COUNTER

#define P_NVC1C0_START_SHADER_PERFORMANCE_COUNTER(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_START_SHADER_PERFORMANCE_COUNTER(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_START_SHADER_PERFORMANCE_COUNTER, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_STOP_SHADER_PERFORMANCE_COUNTER {
    uint32_t counter_mask;
};

static inline void
__NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER(uint32_t *val_out, struct nv_nvc1c0_STOP_SHADER_PERFORMANCE_COUNTER st)
{
    uint32_t val = 0;
    
    assert(st.counter_mask < (UINT64_C(1) << 8));
    val |= st.counter_mask << 0;
    *val_out = val;
}

#define V_NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER(val, args...) { \
    struct nv_nvc1c0_STOP_SHADER_PERFORMANCE_COUNTER __data = { .counter_mask = (args) }; \
    __NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER(&val, __data); \
}

#define VA_NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER V_NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER

#define P_NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER __data = { .v = (args) }; \
    __NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER

#define P_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER {
    uint32_t v;
};

static inline void
__NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER(uint32_t *val_out, struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER(val, args...) { \
    struct nv_nvc1c0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER __data = { .v = (args) }; \
    __NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER(&val, __data); \
}

#define VA_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER

#define P_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER(push, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER, nvk_p_ret); \
} while(0)

struct nv_nvc1c0_SET_MME_SHADOW_SCRATCH {
    uint32_t v;
};

static inline void
__NVC1C0_SET_MME_SHADOW_SCRATCH(uint32_t *val_out, struct nv_nvc1c0_SET_MME_SHADOW_SCRATCH st)
{
    uint32_t val = 0;
    
    val |= st.v;
    *val_out = val;
}

#define V_NVC1C0_SET_MME_SHADOW_SCRATCH(val, args...) { \
    struct nv_nvc1c0_SET_MME_SHADOW_SCRATCH __data = { .v = (args) }; \
    __NVC1C0_SET_MME_SHADOW_SCRATCH(&val, __data); \
}

#define VA_NVC1C0_SET_MME_SHADOW_SCRATCH(i) V_NVC1C0_SET_MME_SHADOW_SCRATCH

#define P_NVC1C0_SET_MME_SHADOW_SCRATCH(push, idx, args...) do { \
    uint32_t nvk_p_ret; \
    V_NVC1C0_SET_MME_SHADOW_SCRATCH(nvk_p_ret, args); \
    nv_push_val(push, NVC1C0_SET_MME_SHADOW_SCRATCH(idx), nvk_p_ret); \
} while(0)


const char *P_PARSE_NVC1C0_MTHD(uint16_t idx) ATTRIBUTE_COLD;
void P_DUMP_NVC1C0_MTHD_DATA(FILE *fp, uint16_t idx, uint32_t data,
                              const char *prefix) ATTRIBUTE_COLD;
