#ifndef REGISTERS_XML
#define REGISTERS_XML

/* Autogenerated file, DO NOT EDIT manually!

This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
http://gitlab.freedesktop.org/mesa/mesa/
git clone https://gitlab.freedesktop.org/mesa/mesa.git

Copyright (C) 2024-2026 by the following authors:
- Tomeu Vizoso <tomeu@tomeuvizoso.net> Tomeu Vizoso

Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:

The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

*/

#ifdef __KERNEL__
#include <linux/bug.h>
#define assert(x) BUG_ON(!(x))
#else
#include <assert.h>
#endif

#ifdef __cplusplus
#define __struct_cast(X)
#else
#define __struct_cast(X) (struct X)
#endif

#define NPU_OP_STOP						0x00000000
#define NPU_OP_STOP_MASK__MASK					0x0000ffff
#define NPU_OP_STOP_MASK__SHIFT					0
static inline uint32_t NPU_OP_STOP_MASK(uint32_t val)
{
	return ((val) << NPU_OP_STOP_MASK__SHIFT) & NPU_OP_STOP_MASK__MASK;
}

#define NPU_OP_IRQ						0x00000001
#define NPU_OP_IRQ_MASK__MASK					0x0000ffff
#define NPU_OP_IRQ_MASK__SHIFT					0
static inline uint32_t NPU_OP_IRQ_MASK(uint32_t val)
{
	return ((val) << NPU_OP_IRQ_MASK__SHIFT) & NPU_OP_IRQ_MASK__MASK;
}

#define NPU_OP_CONV						0x00000002
#define NPU_OP_CONV_RESERVED0__MASK				0x0000ffff
#define NPU_OP_CONV_RESERVED0__SHIFT				0
static inline uint32_t NPU_OP_CONV_RESERVED0(uint32_t val)
{
	return ((val) << NPU_OP_CONV_RESERVED0__SHIFT) & NPU_OP_CONV_RESERVED0__MASK;
}

#define NPU_OP_DEPTHWISE					0x00000003
#define NPU_OP_DEPTHWISE_RESERVED0__MASK			0x0000ffff
#define NPU_OP_DEPTHWISE_RESERVED0__SHIFT			0
static inline uint32_t NPU_OP_DEPTHWISE_RESERVED0(uint32_t val)
{
	return ((val) << NPU_OP_DEPTHWISE_RESERVED0__SHIFT) & NPU_OP_DEPTHWISE_RESERVED0__MASK;
}

#define NPU_OP_POOL						0x00000005
#define NPU_OP_POOL_MODE__MASK					0x0000ffff
#define NPU_OP_POOL_MODE__SHIFT					0
static inline uint32_t NPU_OP_POOL_MODE(uint32_t val)
{
	return ((val) << NPU_OP_POOL_MODE__SHIFT) & NPU_OP_POOL_MODE__MASK;
}

#define NPU_OP_ELEMENTWISE					0x00000006
#define NPU_OP_ELEMENTWISE_MODE__MASK				0x0000ffff
#define NPU_OP_ELEMENTWISE_MODE__SHIFT				0
static inline uint32_t NPU_OP_ELEMENTWISE_MODE(uint32_t val)
{
	return ((val) << NPU_OP_ELEMENTWISE_MODE__SHIFT) & NPU_OP_ELEMENTWISE_MODE__MASK;
}

#define NPU_OP_DMA_START					0x00000010
#define NPU_OP_DMA_START_CHANNEL_MODE__MASK			0x0000ffff
#define NPU_OP_DMA_START_CHANNEL_MODE__SHIFT			0
static inline uint32_t NPU_OP_DMA_START_CHANNEL_MODE(uint32_t val)
{
	return ((val) << NPU_OP_DMA_START_CHANNEL_MODE__SHIFT) & NPU_OP_DMA_START_CHANNEL_MODE__MASK;
}

#define NPU_OP_DMA_WAIT						0x00000011
#define NPU_OP_DMA_WAIT_RESERVED0__MASK				0x0000ffff
#define NPU_OP_DMA_WAIT_RESERVED0__SHIFT			0
static inline uint32_t NPU_OP_DMA_WAIT_RESERVED0(uint32_t val)
{
	return ((val) << NPU_OP_DMA_WAIT_RESERVED0__SHIFT) & NPU_OP_DMA_WAIT_RESERVED0__MASK;
}

#define NPU_OP_KERNEL_WAIT					0x00000012
#define NPU_OP_KERNEL_WAIT_PARAM__MASK				0x0000ffff
#define NPU_OP_KERNEL_WAIT_PARAM__SHIFT				0
static inline uint32_t NPU_OP_KERNEL_WAIT_PARAM(uint32_t val)
{
	return ((val) << NPU_OP_KERNEL_WAIT_PARAM__SHIFT) & NPU_OP_KERNEL_WAIT_PARAM__MASK;
}

#define NPU_OP_PMU_MASK						0x00000013
#define NPU_OP_PMU_MASK_PARAM__MASK				0x0000ffff
#define NPU_OP_PMU_MASK_PARAM__SHIFT				0
static inline uint32_t NPU_OP_PMU_MASK_PARAM(uint32_t val)
{
	return ((val) << NPU_OP_PMU_MASK_PARAM__SHIFT) & NPU_OP_PMU_MASK_PARAM__MASK;
}

#define NPU_SET_IFM_PAD_TOP					0x00000100
#define NPU_SET_IFM_PAD_TOP_PARAM__MASK				0x0000ffff
#define NPU_SET_IFM_PAD_TOP_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM_PAD_TOP_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM_PAD_TOP_PARAM__SHIFT) & NPU_SET_IFM_PAD_TOP_PARAM__MASK;
}

#define NPU_SET_IFM_PAD_LEFT					0x00000101
#define NPU_SET_IFM_PAD_LEFT_PARAM__MASK			0x0000ffff
#define NPU_SET_IFM_PAD_LEFT_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM_PAD_LEFT_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM_PAD_LEFT_PARAM__SHIFT) & NPU_SET_IFM_PAD_LEFT_PARAM__MASK;
}

#define NPU_SET_IFM_PAD_RIGHT					0x00000102
#define NPU_SET_IFM_PAD_RIGHT_PARAM__MASK			0x0000ffff
#define NPU_SET_IFM_PAD_RIGHT_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM_PAD_RIGHT_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM_PAD_RIGHT_PARAM__SHIFT) & NPU_SET_IFM_PAD_RIGHT_PARAM__MASK;
}

#define NPU_SET_IFM_PAD_BOTTOM					0x00000103
#define NPU_SET_IFM_PAD_BOTTOM_PARAM__MASK			0x0000ffff
#define NPU_SET_IFM_PAD_BOTTOM_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM_PAD_BOTTOM_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM_PAD_BOTTOM_PARAM__SHIFT) & NPU_SET_IFM_PAD_BOTTOM_PARAM__MASK;
}

#define NPU_SET_IFM_DEPTH_M1					0x00000104
#define NPU_SET_IFM_DEPTH_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_IFM_DEPTH_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM_DEPTH_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM_DEPTH_M1_PARAM__SHIFT) & NPU_SET_IFM_DEPTH_M1_PARAM__MASK;
}

#define NPU_SET_IFM_PRECISION					0x00000105
#define NPU_SET_IFM_PRECISION_ROUND_MODE__MASK			0x0000c000
#define NPU_SET_IFM_PRECISION_ROUND_MODE__SHIFT			14
static inline uint32_t NPU_SET_IFM_PRECISION_ROUND_MODE(uint32_t val)
{
	return ((val) << NPU_SET_IFM_PRECISION_ROUND_MODE__SHIFT) & NPU_SET_IFM_PRECISION_ROUND_MODE__MASK;
}
#define NPU_SET_IFM_PRECISION_RESERVED2__MASK			0x00003c00
#define NPU_SET_IFM_PRECISION_RESERVED2__SHIFT			10
static inline uint32_t NPU_SET_IFM_PRECISION_RESERVED2(uint32_t val)
{
	return ((val) << NPU_SET_IFM_PRECISION_RESERVED2__SHIFT) & NPU_SET_IFM_PRECISION_RESERVED2__MASK;
}
#define NPU_SET_IFM_PRECISION_SCALE_MODE__MASK			0x00000300
#define NPU_SET_IFM_PRECISION_SCALE_MODE__SHIFT			8
static inline uint32_t NPU_SET_IFM_PRECISION_SCALE_MODE(uint32_t val)
{
	return ((val) << NPU_SET_IFM_PRECISION_SCALE_MODE__SHIFT) & NPU_SET_IFM_PRECISION_SCALE_MODE__MASK;
}
#define NPU_SET_IFM_PRECISION_FORMAT__MASK			0x000000c0
#define NPU_SET_IFM_PRECISION_FORMAT__SHIFT			6
static inline uint32_t NPU_SET_IFM_PRECISION_FORMAT(uint32_t val)
{
	return ((val) << NPU_SET_IFM_PRECISION_FORMAT__SHIFT) & NPU_SET_IFM_PRECISION_FORMAT__MASK;
}
#define NPU_SET_IFM_PRECISION_RESERVED1__MASK			0x00000030
#define NPU_SET_IFM_PRECISION_RESERVED1__SHIFT			4
static inline uint32_t NPU_SET_IFM_PRECISION_RESERVED1(uint32_t val)
{
	return ((val) << NPU_SET_IFM_PRECISION_RESERVED1__SHIFT) & NPU_SET_IFM_PRECISION_RESERVED1__MASK;
}
#define NPU_SET_IFM_PRECISION_PRECISION__MASK			0x0000000c
#define NPU_SET_IFM_PRECISION_PRECISION__SHIFT			2
static inline uint32_t NPU_SET_IFM_PRECISION_PRECISION(uint32_t val)
{
	return ((val) << NPU_SET_IFM_PRECISION_PRECISION__SHIFT) & NPU_SET_IFM_PRECISION_PRECISION__MASK;
}
#define NPU_SET_IFM_PRECISION_RESERVED0__MASK			0x00000002
#define NPU_SET_IFM_PRECISION_RESERVED0__SHIFT			1
static inline uint32_t NPU_SET_IFM_PRECISION_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM_PRECISION_RESERVED0__SHIFT) & NPU_SET_IFM_PRECISION_RESERVED0__MASK;
}
#define NPU_SET_IFM_PRECISION_ACTIVATION__MASK			0x00000001
#define NPU_SET_IFM_PRECISION_ACTIVATION__SHIFT			0
static inline uint32_t NPU_SET_IFM_PRECISION_ACTIVATION(uint32_t val)
{
	return ((val) << NPU_SET_IFM_PRECISION_ACTIVATION__SHIFT) & NPU_SET_IFM_PRECISION_ACTIVATION__MASK;
}

#define NPU_SET_IFM_UPSCALE					0x00000107
#define NPU_SET_IFM_UPSCALE_RESERVED0__MASK			0x0000fffc
#define NPU_SET_IFM_UPSCALE_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_IFM_UPSCALE_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM_UPSCALE_RESERVED0__SHIFT) & NPU_SET_IFM_UPSCALE_RESERVED0__MASK;
}
#define NPU_SET_IFM_UPSCALE_MODE__MASK				0x00000003
#define NPU_SET_IFM_UPSCALE_MODE__SHIFT				0
static inline uint32_t NPU_SET_IFM_UPSCALE_MODE(uint32_t val)
{
	return ((val) << NPU_SET_IFM_UPSCALE_MODE__SHIFT) & NPU_SET_IFM_UPSCALE_MODE__MASK;
}

#define NPU_SET_IFM_BROADCAST					0x00000108
#define NPU_SET_IFM_BROADCAST_RESERVED1__MASK			0x0000ff00
#define NPU_SET_IFM_BROADCAST_RESERVED1__SHIFT			8
static inline uint32_t NPU_SET_IFM_BROADCAST_RESERVED1(uint32_t val)
{
	return ((val) << NPU_SET_IFM_BROADCAST_RESERVED1__SHIFT) & NPU_SET_IFM_BROADCAST_RESERVED1__MASK;
}
#define NPU_SET_IFM_BROADCAST_BROADCAST_SCALAR__MASK		0x00000080
#define NPU_SET_IFM_BROADCAST_BROADCAST_SCALAR__SHIFT		7
static inline uint32_t NPU_SET_IFM_BROADCAST_BROADCAST_SCALAR(uint32_t val)
{
	return ((val) << NPU_SET_IFM_BROADCAST_BROADCAST_SCALAR__SHIFT) & NPU_SET_IFM_BROADCAST_BROADCAST_SCALAR__MASK;
}
#define NPU_SET_IFM_BROADCAST_OPERAND_ORDER__MASK		0x00000040
#define NPU_SET_IFM_BROADCAST_OPERAND_ORDER__SHIFT		6
static inline uint32_t NPU_SET_IFM_BROADCAST_OPERAND_ORDER(uint32_t val)
{
	return ((val) << NPU_SET_IFM_BROADCAST_OPERAND_ORDER__SHIFT) & NPU_SET_IFM_BROADCAST_OPERAND_ORDER__MASK;
}
#define NPU_SET_IFM_BROADCAST_RESERVED0__MASK			0x00000038
#define NPU_SET_IFM_BROADCAST_RESERVED0__SHIFT			3
static inline uint32_t NPU_SET_IFM_BROADCAST_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM_BROADCAST_RESERVED0__SHIFT) & NPU_SET_IFM_BROADCAST_RESERVED0__MASK;
}
#define NPU_SET_IFM_BROADCAST_BROADCAST_DEPTH__MASK		0x00000004
#define NPU_SET_IFM_BROADCAST_BROADCAST_DEPTH__SHIFT		2
static inline uint32_t NPU_SET_IFM_BROADCAST_BROADCAST_DEPTH(uint32_t val)
{
	return ((val) << NPU_SET_IFM_BROADCAST_BROADCAST_DEPTH__SHIFT) & NPU_SET_IFM_BROADCAST_BROADCAST_DEPTH__MASK;
}
#define NPU_SET_IFM_BROADCAST_BROADCAST_WIDTH__MASK		0x00000002
#define NPU_SET_IFM_BROADCAST_BROADCAST_WIDTH__SHIFT		1
static inline uint32_t NPU_SET_IFM_BROADCAST_BROADCAST_WIDTH(uint32_t val)
{
	return ((val) << NPU_SET_IFM_BROADCAST_BROADCAST_WIDTH__SHIFT) & NPU_SET_IFM_BROADCAST_BROADCAST_WIDTH__MASK;
}
#define NPU_SET_IFM_BROADCAST_BROADCAST_HEIGHT__MASK		0x00000001
#define NPU_SET_IFM_BROADCAST_BROADCAST_HEIGHT__SHIFT		0
static inline uint32_t NPU_SET_IFM_BROADCAST_BROADCAST_HEIGHT(uint32_t val)
{
	return ((val) << NPU_SET_IFM_BROADCAST_BROADCAST_HEIGHT__SHIFT) & NPU_SET_IFM_BROADCAST_BROADCAST_HEIGHT__MASK;
}

#define NPU_SET_IFM_ZERO_POINT					0x00000109
#define NPU_SET_IFM_ZERO_POINT_PARAM__MASK			0x0000ffff
#define NPU_SET_IFM_ZERO_POINT_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM_ZERO_POINT_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM_ZERO_POINT_PARAM__SHIFT) & NPU_SET_IFM_ZERO_POINT_PARAM__MASK;
}

#define NPU_SET_IFM_WIDTH0_M1					0x0000010a
#define NPU_SET_IFM_WIDTH0_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_IFM_WIDTH0_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM_WIDTH0_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM_WIDTH0_M1_PARAM__SHIFT) & NPU_SET_IFM_WIDTH0_M1_PARAM__MASK;
}

#define NPU_SET_IFM_HEIGHT0_M1					0x0000010b
#define NPU_SET_IFM_HEIGHT0_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_IFM_HEIGHT0_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM_HEIGHT0_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM_HEIGHT0_M1_PARAM__SHIFT) & NPU_SET_IFM_HEIGHT0_M1_PARAM__MASK;
}

#define NPU_SET_IFM_HEIGHT1_M1					0x0000010c
#define NPU_SET_IFM_HEIGHT1_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_IFM_HEIGHT1_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM_HEIGHT1_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM_HEIGHT1_M1_PARAM__SHIFT) & NPU_SET_IFM_HEIGHT1_M1_PARAM__MASK;
}

#define NPU_SET_IFM_IB_END					0x0000010d
#define NPU_SET_IFM_IB_END_PARAM__MASK				0x0000ffff
#define NPU_SET_IFM_IB_END_PARAM__SHIFT				0
static inline uint32_t NPU_SET_IFM_IB_END_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM_IB_END_PARAM__SHIFT) & NPU_SET_IFM_IB_END_PARAM__MASK;
}

#define NPU_SET_IFM_REGION					0x0000010f
#define NPU_SET_IFM_REGION_PARAM__MASK				0x0000ffff
#define NPU_SET_IFM_REGION_PARAM__SHIFT				0
static inline uint32_t NPU_SET_IFM_REGION_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM_REGION_PARAM__SHIFT) & NPU_SET_IFM_REGION_PARAM__MASK;
}

#define NPU_SET_OFM_WIDTH_M1					0x00000111
#define NPU_SET_OFM_WIDTH_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_OFM_WIDTH_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_OFM_WIDTH_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_OFM_WIDTH_M1_PARAM__SHIFT) & NPU_SET_OFM_WIDTH_M1_PARAM__MASK;
}

#define NPU_SET_OFM_HEIGHT_M1					0x00000112
#define NPU_SET_OFM_HEIGHT_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_OFM_HEIGHT_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_OFM_HEIGHT_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_OFM_HEIGHT_M1_PARAM__SHIFT) & NPU_SET_OFM_HEIGHT_M1_PARAM__MASK;
}

#define NPU_SET_OFM_DEPTH_M1					0x00000113
#define NPU_SET_OFM_DEPTH_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_OFM_DEPTH_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_OFM_DEPTH_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_OFM_DEPTH_M1_PARAM__SHIFT) & NPU_SET_OFM_DEPTH_M1_PARAM__MASK;
}

#define NPU_SET_OFM_PRECISION					0x00000114
#define NPU_SET_OFM_PRECISION_ROUND_MODE__MASK			0x0000c000
#define NPU_SET_OFM_PRECISION_ROUND_MODE__SHIFT			14
static inline uint32_t NPU_SET_OFM_PRECISION_ROUND_MODE(uint32_t val)
{
	return ((val) << NPU_SET_OFM_PRECISION_ROUND_MODE__SHIFT) & NPU_SET_OFM_PRECISION_ROUND_MODE__MASK;
}
#define NPU_SET_OFM_PRECISION_RESERVED1__MASK			0x00003e00
#define NPU_SET_OFM_PRECISION_RESERVED1__SHIFT			9
static inline uint32_t NPU_SET_OFM_PRECISION_RESERVED1(uint32_t val)
{
	return ((val) << NPU_SET_OFM_PRECISION_RESERVED1__SHIFT) & NPU_SET_OFM_PRECISION_RESERVED1__MASK;
}
#define NPU_SET_OFM_PRECISION_SCALE_MODE__MASK			0x00000100
#define NPU_SET_OFM_PRECISION_SCALE_MODE__SHIFT			8
static inline uint32_t NPU_SET_OFM_PRECISION_SCALE_MODE(uint32_t val)
{
	return ((val) << NPU_SET_OFM_PRECISION_SCALE_MODE__SHIFT) & NPU_SET_OFM_PRECISION_SCALE_MODE__MASK;
}
#define NPU_SET_OFM_PRECISION_FORMAT__MASK			0x000000c0
#define NPU_SET_OFM_PRECISION_FORMAT__SHIFT			6
static inline uint32_t NPU_SET_OFM_PRECISION_FORMAT(uint32_t val)
{
	return ((val) << NPU_SET_OFM_PRECISION_FORMAT__SHIFT) & NPU_SET_OFM_PRECISION_FORMAT__MASK;
}
#define NPU_SET_OFM_PRECISION_RESERVED0__MASK			0x00000038
#define NPU_SET_OFM_PRECISION_RESERVED0__SHIFT			3
static inline uint32_t NPU_SET_OFM_PRECISION_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_OFM_PRECISION_RESERVED0__SHIFT) & NPU_SET_OFM_PRECISION_RESERVED0__MASK;
}
#define NPU_SET_OFM_PRECISION_PRECISION__MASK			0x00000006
#define NPU_SET_OFM_PRECISION_PRECISION__SHIFT			1
static inline uint32_t NPU_SET_OFM_PRECISION_PRECISION(uint32_t val)
{
	return ((val) << NPU_SET_OFM_PRECISION_PRECISION__SHIFT) & NPU_SET_OFM_PRECISION_PRECISION__MASK;
}
#define NPU_SET_OFM_PRECISION_ACTIVATION__MASK			0x00000001
#define NPU_SET_OFM_PRECISION_ACTIVATION__SHIFT			0
static inline uint32_t NPU_SET_OFM_PRECISION_ACTIVATION(uint32_t val)
{
	return ((val) << NPU_SET_OFM_PRECISION_ACTIVATION__SHIFT) & NPU_SET_OFM_PRECISION_ACTIVATION__MASK;
}

#define NPU_SET_OFM_BLK_WIDTH_M1				0x00000115
#define NPU_SET_OFM_BLK_WIDTH_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_OFM_BLK_WIDTH_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_OFM_BLK_WIDTH_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_OFM_BLK_WIDTH_M1_PARAM__SHIFT) & NPU_SET_OFM_BLK_WIDTH_M1_PARAM__MASK;
}

#define NPU_SET_OFM_BLK_HEIGHT_M1				0x00000116
#define NPU_SET_OFM_BLK_HEIGHT_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_OFM_BLK_HEIGHT_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_OFM_BLK_HEIGHT_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_OFM_BLK_HEIGHT_M1_PARAM__SHIFT) & NPU_SET_OFM_BLK_HEIGHT_M1_PARAM__MASK;
}

#define NPU_SET_OFM_BLK_DEPTH_M1				0x00000117
#define NPU_SET_OFM_BLK_DEPTH_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_OFM_BLK_DEPTH_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_OFM_BLK_DEPTH_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_OFM_BLK_DEPTH_M1_PARAM__SHIFT) & NPU_SET_OFM_BLK_DEPTH_M1_PARAM__MASK;
}

#define NPU_SET_OFM_ZERO_POINT					0x00000118
#define NPU_SET_OFM_ZERO_POINT_PARAM__MASK			0x0000ffff
#define NPU_SET_OFM_ZERO_POINT_PARAM__SHIFT			0
static inline uint32_t NPU_SET_OFM_ZERO_POINT_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_OFM_ZERO_POINT_PARAM__SHIFT) & NPU_SET_OFM_ZERO_POINT_PARAM__MASK;
}

#define NPU_SET_OFM_WIDTH0_M1					0x0000011a
#define NPU_SET_OFM_WIDTH0_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_OFM_WIDTH0_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_OFM_WIDTH0_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_OFM_WIDTH0_M1_PARAM__SHIFT) & NPU_SET_OFM_WIDTH0_M1_PARAM__MASK;
}

#define NPU_SET_OFM_HEIGHT0_M1					0x0000011b
#define NPU_SET_OFM_HEIGHT0_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_OFM_HEIGHT0_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_OFM_HEIGHT0_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_OFM_HEIGHT0_M1_PARAM__SHIFT) & NPU_SET_OFM_HEIGHT0_M1_PARAM__MASK;
}

#define NPU_SET_OFM_HEIGHT1_M1					0x0000011c
#define NPU_SET_OFM_HEIGHT1_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_OFM_HEIGHT1_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_OFM_HEIGHT1_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_OFM_HEIGHT1_M1_PARAM__SHIFT) & NPU_SET_OFM_HEIGHT1_M1_PARAM__MASK;
}

#define NPU_SET_OFM_REGION					0x0000011f
#define NPU_SET_OFM_REGION_PARAM__MASK				0x0000ffff
#define NPU_SET_OFM_REGION_PARAM__SHIFT				0
static inline uint32_t NPU_SET_OFM_REGION_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_OFM_REGION_PARAM__SHIFT) & NPU_SET_OFM_REGION_PARAM__MASK;
}

#define NPU_SET_KERNEL_WIDTH_M1					0x00000120
#define NPU_SET_KERNEL_WIDTH_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_KERNEL_WIDTH_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_KERNEL_WIDTH_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_KERNEL_WIDTH_M1_PARAM__SHIFT) & NPU_SET_KERNEL_WIDTH_M1_PARAM__MASK;
}

#define NPU_SET_KERNEL_HEIGHT_M1				0x00000121
#define NPU_SET_KERNEL_HEIGHT_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_KERNEL_HEIGHT_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_KERNEL_HEIGHT_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_KERNEL_HEIGHT_M1_PARAM__SHIFT) & NPU_SET_KERNEL_HEIGHT_M1_PARAM__MASK;
}

#define NPU_SET_KERNEL_STRIDE					0x00000122
#define NPU_SET_KERNEL_STRIDE_PARAM__MASK			0x0000ffff
#define NPU_SET_KERNEL_STRIDE_PARAM__SHIFT			0
static inline uint32_t NPU_SET_KERNEL_STRIDE_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_KERNEL_STRIDE_PARAM__SHIFT) & NPU_SET_KERNEL_STRIDE_PARAM__MASK;
}

#define NPU_SET_PARALLEL_MODE					0x00000123
#define NPU_SET_PARALLEL_MODE_PARAM__MASK			0x0000ffff
#define NPU_SET_PARALLEL_MODE_PARAM__SHIFT			0
static inline uint32_t NPU_SET_PARALLEL_MODE_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_PARALLEL_MODE_PARAM__SHIFT) & NPU_SET_PARALLEL_MODE_PARAM__MASK;
}

#define NPU_SET_ACC_FORMAT					0x00000124
#define NPU_SET_ACC_FORMAT_RESERVED3__MASK			0x0000f800
#define NPU_SET_ACC_FORMAT_RESERVED3__SHIFT			11
static inline uint32_t NPU_SET_ACC_FORMAT_RESERVED3(uint32_t val)
{
	return ((val) << NPU_SET_ACC_FORMAT_RESERVED3__SHIFT) & NPU_SET_ACC_FORMAT_RESERVED3__MASK;
}
#define NPU_SET_ACC_FORMAT_MICROBLOCK__MASK			0x00000700
#define NPU_SET_ACC_FORMAT_MICROBLOCK__SHIFT			8
static inline uint32_t NPU_SET_ACC_FORMAT_MICROBLOCK(uint32_t val)
{
	return ((val) << NPU_SET_ACC_FORMAT_MICROBLOCK__SHIFT) & NPU_SET_ACC_FORMAT_MICROBLOCK__MASK;
}
#define NPU_SET_ACC_FORMAT_RESERVED2__MASK			0x00000080
#define NPU_SET_ACC_FORMAT_RESERVED2__SHIFT			7
static inline uint32_t NPU_SET_ACC_FORMAT_RESERVED2(uint32_t val)
{
	return ((val) << NPU_SET_ACC_FORMAT_RESERVED2__SHIFT) & NPU_SET_ACC_FORMAT_RESERVED2__MASK;
}
#define NPU_SET_ACC_FORMAT_ACC_OUTPUT__MASK			0x00000040
#define NPU_SET_ACC_FORMAT_ACC_OUTPUT__SHIFT			6
static inline uint32_t NPU_SET_ACC_FORMAT_ACC_OUTPUT(uint32_t val)
{
	return ((val) << NPU_SET_ACC_FORMAT_ACC_OUTPUT__SHIFT) & NPU_SET_ACC_FORMAT_ACC_OUTPUT__MASK;
}
#define NPU_SET_ACC_FORMAT_ACC_INPUT__MASK			0x00000030
#define NPU_SET_ACC_FORMAT_ACC_INPUT__SHIFT			4
static inline uint32_t NPU_SET_ACC_FORMAT_ACC_INPUT(uint32_t val)
{
	return ((val) << NPU_SET_ACC_FORMAT_ACC_INPUT__SHIFT) & NPU_SET_ACC_FORMAT_ACC_INPUT__MASK;
}
#define NPU_SET_ACC_FORMAT_RESERVED1__MASK			0x0000000c
#define NPU_SET_ACC_FORMAT_RESERVED1__SHIFT			2
static inline uint32_t NPU_SET_ACC_FORMAT_RESERVED1(uint32_t val)
{
	return ((val) << NPU_SET_ACC_FORMAT_RESERVED1__SHIFT) & NPU_SET_ACC_FORMAT_RESERVED1__MASK;
}
#define NPU_SET_ACC_FORMAT_ACC_FORMAT__MASK			0x00000003
#define NPU_SET_ACC_FORMAT_ACC_FORMAT__SHIFT			0
static inline uint32_t NPU_SET_ACC_FORMAT_ACC_FORMAT(uint32_t val)
{
	return ((val) << NPU_SET_ACC_FORMAT_ACC_FORMAT__SHIFT) & NPU_SET_ACC_FORMAT_ACC_FORMAT__MASK;
}

#define NPU_SET_ACTIVATION					0x00000125
#define NPU_SET_ACTIVATION_ACT_CLIP_RANGE__MASK			0x0000f000
#define NPU_SET_ACTIVATION_ACT_CLIP_RANGE__SHIFT		12
static inline uint32_t NPU_SET_ACTIVATION_ACT_CLIP_RANGE(uint32_t val)
{
	return ((val) << NPU_SET_ACTIVATION_ACT_CLIP_RANGE__SHIFT) & NPU_SET_ACTIVATION_ACT_CLIP_RANGE__MASK;
}
#define NPU_SET_ACTIVATION_TYPE__MASK				0x00000fff
#define NPU_SET_ACTIVATION_TYPE__SHIFT				0
static inline uint32_t NPU_SET_ACTIVATION_TYPE(uint32_t val)
{
	return ((val) << NPU_SET_ACTIVATION_TYPE__SHIFT) & NPU_SET_ACTIVATION_TYPE__MASK;
}

#define NPU_SET_ACTIVATION_MIN					0x00000126
#define NPU_SET_ACTIVATION_MIN_PARAM__MASK			0x0000ffff
#define NPU_SET_ACTIVATION_MIN_PARAM__SHIFT			0
static inline uint32_t NPU_SET_ACTIVATION_MIN_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_ACTIVATION_MIN_PARAM__SHIFT) & NPU_SET_ACTIVATION_MIN_PARAM__MASK;
}

#define NPU_SET_ACTIVATION_MAX					0x00000127
#define NPU_SET_ACTIVATION_MAX_PARAM__MASK			0x0000ffff
#define NPU_SET_ACTIVATION_MAX_PARAM__SHIFT			0
static inline uint32_t NPU_SET_ACTIVATION_MAX_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_ACTIVATION_MAX_PARAM__SHIFT) & NPU_SET_ACTIVATION_MAX_PARAM__MASK;
}

#define NPU_SET_WEIGHT_REGION					0x00000128
#define NPU_SET_WEIGHT_REGION_PARAM__MASK			0x0000ffff
#define NPU_SET_WEIGHT_REGION_PARAM__SHIFT			0
static inline uint32_t NPU_SET_WEIGHT_REGION_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_WEIGHT_REGION_PARAM__SHIFT) & NPU_SET_WEIGHT_REGION_PARAM__MASK;
}

#define NPU_SET_SCALE_REGION					0x00000129
#define NPU_SET_SCALE_REGION_PARAM__MASK			0x0000ffff
#define NPU_SET_SCALE_REGION_PARAM__SHIFT			0
static inline uint32_t NPU_SET_SCALE_REGION_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_SCALE_REGION_PARAM__SHIFT) & NPU_SET_SCALE_REGION_PARAM__MASK;
}

#define NPU_SET_AB_START					0x0000012d
#define NPU_SET_AB_START_PARAM__MASK				0x0000ffff
#define NPU_SET_AB_START_PARAM__SHIFT				0
static inline uint32_t NPU_SET_AB_START_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_AB_START_PARAM__SHIFT) & NPU_SET_AB_START_PARAM__MASK;
}

#define NPU_SET_WEIGHT_FORMAT					0x0000012e
#define NPU_SET_WEIGHT_FORMAT_RESERVED1__MASK			0x0000ffe0
#define NPU_SET_WEIGHT_FORMAT_RESERVED1__SHIFT			5
static inline uint32_t NPU_SET_WEIGHT_FORMAT_RESERVED1(uint32_t val)
{
	return ((val) << NPU_SET_WEIGHT_FORMAT_RESERVED1__SHIFT) & NPU_SET_WEIGHT_FORMAT_RESERVED1__MASK;
}
#define NPU_SET_WEIGHT_FORMAT_SPARSITY__MASK			0x00000010
#define NPU_SET_WEIGHT_FORMAT_SPARSITY__SHIFT			4
static inline uint32_t NPU_SET_WEIGHT_FORMAT_SPARSITY(uint32_t val)
{
	return ((val) << NPU_SET_WEIGHT_FORMAT_SPARSITY__SHIFT) & NPU_SET_WEIGHT_FORMAT_SPARSITY__MASK;
}
#define NPU_SET_WEIGHT_FORMAT_RESERVED0__MASK			0x0000000e
#define NPU_SET_WEIGHT_FORMAT_RESERVED0__SHIFT			1
static inline uint32_t NPU_SET_WEIGHT_FORMAT_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_WEIGHT_FORMAT_RESERVED0__SHIFT) & NPU_SET_WEIGHT_FORMAT_RESERVED0__MASK;
}
#define NPU_SET_WEIGHT_FORMAT_FORMAT__MASK			0x00000001
#define NPU_SET_WEIGHT_FORMAT_FORMAT__SHIFT			0
static inline uint32_t NPU_SET_WEIGHT_FORMAT_FORMAT(uint32_t val)
{
	return ((val) << NPU_SET_WEIGHT_FORMAT_FORMAT__SHIFT) & NPU_SET_WEIGHT_FORMAT_FORMAT__MASK;
}

#define NPU_SET_BLOCKDEP					0x0000012f
#define NPU_SET_BLOCKDEP_PARAM__MASK				0x0000ffff
#define NPU_SET_BLOCKDEP_PARAM__SHIFT				0
static inline uint32_t NPU_SET_BLOCKDEP_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_BLOCKDEP_PARAM__SHIFT) & NPU_SET_BLOCKDEP_PARAM__MASK;
}

#define NPU_SET_DMA0_SRC_REGION					0x00000130
#define NPU_SET_DMA0_SRC_REGION_RESERVED0__MASK			0x0000f800
#define NPU_SET_DMA0_SRC_REGION_RESERVED0__SHIFT		11
static inline uint32_t NPU_SET_DMA0_SRC_REGION_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_SRC_REGION_RESERVED0__SHIFT) & NPU_SET_DMA0_SRC_REGION_RESERVED0__MASK;
}
#define NPU_SET_DMA0_SRC_REGION_STRIDE_MODE__MASK		0x00000600
#define NPU_SET_DMA0_SRC_REGION_STRIDE_MODE__SHIFT		9
static inline uint32_t NPU_SET_DMA0_SRC_REGION_STRIDE_MODE(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_SRC_REGION_STRIDE_MODE__SHIFT) & NPU_SET_DMA0_SRC_REGION_STRIDE_MODE__MASK;
}
#define NPU_SET_DMA0_SRC_REGION_INTERNAL__MASK			0x00000100
#define NPU_SET_DMA0_SRC_REGION_INTERNAL__SHIFT			8
static inline uint32_t NPU_SET_DMA0_SRC_REGION_INTERNAL(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_SRC_REGION_INTERNAL__SHIFT) & NPU_SET_DMA0_SRC_REGION_INTERNAL__MASK;
}
#define NPU_SET_DMA0_SRC_REGION_REGION__MASK			0x000000ff
#define NPU_SET_DMA0_SRC_REGION_REGION__SHIFT			0
static inline uint32_t NPU_SET_DMA0_SRC_REGION_REGION(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_SRC_REGION_REGION__SHIFT) & NPU_SET_DMA0_SRC_REGION_REGION__MASK;
}

#define NPU_SET_DMA0_DST_REGION					0x00000131
#define NPU_SET_DMA0_DST_REGION_RESERVED0__MASK			0x0000f800
#define NPU_SET_DMA0_DST_REGION_RESERVED0__SHIFT		11
static inline uint32_t NPU_SET_DMA0_DST_REGION_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_DST_REGION_RESERVED0__SHIFT) & NPU_SET_DMA0_DST_REGION_RESERVED0__MASK;
}
#define NPU_SET_DMA0_DST_REGION_STRIDE_MODE__MASK		0x00000600
#define NPU_SET_DMA0_DST_REGION_STRIDE_MODE__SHIFT		9
static inline uint32_t NPU_SET_DMA0_DST_REGION_STRIDE_MODE(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_DST_REGION_STRIDE_MODE__SHIFT) & NPU_SET_DMA0_DST_REGION_STRIDE_MODE__MASK;
}
#define NPU_SET_DMA0_DST_REGION_INTERNAL__MASK			0x00000100
#define NPU_SET_DMA0_DST_REGION_INTERNAL__SHIFT			8
static inline uint32_t NPU_SET_DMA0_DST_REGION_INTERNAL(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_DST_REGION_INTERNAL__SHIFT) & NPU_SET_DMA0_DST_REGION_INTERNAL__MASK;
}
#define NPU_SET_DMA0_DST_REGION_REGION__MASK			0x000000ff
#define NPU_SET_DMA0_DST_REGION_REGION__SHIFT			0
static inline uint32_t NPU_SET_DMA0_DST_REGION_REGION(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_DST_REGION_REGION__SHIFT) & NPU_SET_DMA0_DST_REGION_REGION__MASK;
}

#define NPU_SET_DMA0_SIZE0					0x00000132
#define NPU_SET_DMA0_SIZE0_PARAM__MASK				0x0000ffff
#define NPU_SET_DMA0_SIZE0_PARAM__SHIFT				0
static inline uint32_t NPU_SET_DMA0_SIZE0_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_SIZE0_PARAM__SHIFT) & NPU_SET_DMA0_SIZE0_PARAM__MASK;
}

#define NPU_SET_DMA0_SIZE1					0x00000133
#define NPU_SET_DMA0_SIZE1_PARAM__MASK				0x0000ffff
#define NPU_SET_DMA0_SIZE1_PARAM__SHIFT				0
static inline uint32_t NPU_SET_DMA0_SIZE1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_SIZE1_PARAM__SHIFT) & NPU_SET_DMA0_SIZE1_PARAM__MASK;
}

#define NPU_SET_IFM2_BROADCAST					0x00000180
#define NPU_SET_IFM2_BROADCAST_RESERVED1__MASK			0x0000ff00
#define NPU_SET_IFM2_BROADCAST_RESERVED1__SHIFT			8
static inline uint32_t NPU_SET_IFM2_BROADCAST_RESERVED1(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_BROADCAST_RESERVED1__SHIFT) & NPU_SET_IFM2_BROADCAST_RESERVED1__MASK;
}
#define NPU_SET_IFM2_BROADCAST_BROADCAST_SCALAR__MASK		0x00000080
#define NPU_SET_IFM2_BROADCAST_BROADCAST_SCALAR__SHIFT		7
static inline uint32_t NPU_SET_IFM2_BROADCAST_BROADCAST_SCALAR(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_BROADCAST_BROADCAST_SCALAR__SHIFT) & NPU_SET_IFM2_BROADCAST_BROADCAST_SCALAR__MASK;
}
#define NPU_SET_IFM2_BROADCAST_OPERAND_ORDER__MASK		0x00000040
#define NPU_SET_IFM2_BROADCAST_OPERAND_ORDER__SHIFT		6
static inline uint32_t NPU_SET_IFM2_BROADCAST_OPERAND_ORDER(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_BROADCAST_OPERAND_ORDER__SHIFT) & NPU_SET_IFM2_BROADCAST_OPERAND_ORDER__MASK;
}
#define NPU_SET_IFM2_BROADCAST_RESERVED0__MASK			0x00000038
#define NPU_SET_IFM2_BROADCAST_RESERVED0__SHIFT			3
static inline uint32_t NPU_SET_IFM2_BROADCAST_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_BROADCAST_RESERVED0__SHIFT) & NPU_SET_IFM2_BROADCAST_RESERVED0__MASK;
}
#define NPU_SET_IFM2_BROADCAST_BROADCAST_DEPTH__MASK		0x00000004
#define NPU_SET_IFM2_BROADCAST_BROADCAST_DEPTH__SHIFT		2
static inline uint32_t NPU_SET_IFM2_BROADCAST_BROADCAST_DEPTH(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_BROADCAST_BROADCAST_DEPTH__SHIFT) & NPU_SET_IFM2_BROADCAST_BROADCAST_DEPTH__MASK;
}
#define NPU_SET_IFM2_BROADCAST_BROADCAST_WIDTH__MASK		0x00000002
#define NPU_SET_IFM2_BROADCAST_BROADCAST_WIDTH__SHIFT		1
static inline uint32_t NPU_SET_IFM2_BROADCAST_BROADCAST_WIDTH(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_BROADCAST_BROADCAST_WIDTH__SHIFT) & NPU_SET_IFM2_BROADCAST_BROADCAST_WIDTH__MASK;
}
#define NPU_SET_IFM2_BROADCAST_BROADCAST_HEIGHT__MASK		0x00000001
#define NPU_SET_IFM2_BROADCAST_BROADCAST_HEIGHT__SHIFT		0
static inline uint32_t NPU_SET_IFM2_BROADCAST_BROADCAST_HEIGHT(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_BROADCAST_BROADCAST_HEIGHT__SHIFT) & NPU_SET_IFM2_BROADCAST_BROADCAST_HEIGHT__MASK;
}

#define NPU_SET_IFM2_SCALAR					0x00000181
#define NPU_SET_IFM2_SCALAR_PARAM__MASK				0x0000ffff
#define NPU_SET_IFM2_SCALAR_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM2_SCALAR_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_SCALAR_PARAM__SHIFT) & NPU_SET_IFM2_SCALAR_PARAM__MASK;
}

#define NPU_SET_IFM2_PRECISION					0x00000185
#define NPU_SET_IFM2_PRECISION_ACTIVATION_STORAGE__MASK		0x0000c000
#define NPU_SET_IFM2_PRECISION_ACTIVATION_STORAGE__SHIFT	14
static inline uint32_t NPU_SET_IFM2_PRECISION_ACTIVATION_STORAGE(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_PRECISION_ACTIVATION_STORAGE__SHIFT) & NPU_SET_IFM2_PRECISION_ACTIVATION_STORAGE__MASK;
}
#define NPU_SET_IFM2_PRECISION_RESERVED3__MASK			0x00003f00
#define NPU_SET_IFM2_PRECISION_RESERVED3__SHIFT			8
static inline uint32_t NPU_SET_IFM2_PRECISION_RESERVED3(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_PRECISION_RESERVED3__SHIFT) & NPU_SET_IFM2_PRECISION_RESERVED3__MASK;
}
#define NPU_SET_IFM2_PRECISION_ACTIVATION_FORMAT__MASK		0x000000c0
#define NPU_SET_IFM2_PRECISION_ACTIVATION_FORMAT__SHIFT		6
static inline uint32_t NPU_SET_IFM2_PRECISION_ACTIVATION_FORMAT(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_PRECISION_ACTIVATION_FORMAT__SHIFT) & NPU_SET_IFM2_PRECISION_ACTIVATION_FORMAT__MASK;
}
#define NPU_SET_IFM2_PRECISION_RESERVED2__MASK			0x00000030
#define NPU_SET_IFM2_PRECISION_RESERVED2__SHIFT			4
static inline uint32_t NPU_SET_IFM2_PRECISION_RESERVED2(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_PRECISION_RESERVED2__SHIFT) & NPU_SET_IFM2_PRECISION_RESERVED2__MASK;
}
#define NPU_SET_IFM2_PRECISION_ACTIVATION_PRECISION__MASK	0x0000000c
#define NPU_SET_IFM2_PRECISION_ACTIVATION_PRECISION__SHIFT	2
static inline uint32_t NPU_SET_IFM2_PRECISION_ACTIVATION_PRECISION(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_PRECISION_ACTIVATION_PRECISION__SHIFT) & NPU_SET_IFM2_PRECISION_ACTIVATION_PRECISION__MASK;
}
#define NPU_SET_IFM2_PRECISION_RESERVED1__MASK			0x00000002
#define NPU_SET_IFM2_PRECISION_RESERVED1__SHIFT			1
static inline uint32_t NPU_SET_IFM2_PRECISION_RESERVED1(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_PRECISION_RESERVED1__SHIFT) & NPU_SET_IFM2_PRECISION_RESERVED1__MASK;
}
#define NPU_SET_IFM2_PRECISION_ACTIVATION_TYPE__MASK		0x00000001
#define NPU_SET_IFM2_PRECISION_ACTIVATION_TYPE__SHIFT		0
static inline uint32_t NPU_SET_IFM2_PRECISION_ACTIVATION_TYPE(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_PRECISION_ACTIVATION_TYPE__SHIFT) & NPU_SET_IFM2_PRECISION_ACTIVATION_TYPE__MASK;
}

#define NPU_SET_IFM2_ZERO_POINT					0x00000189
#define NPU_SET_IFM2_ZERO_POINT_PARAM__MASK			0x0000ffff
#define NPU_SET_IFM2_ZERO_POINT_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM2_ZERO_POINT_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_ZERO_POINT_PARAM__SHIFT) & NPU_SET_IFM2_ZERO_POINT_PARAM__MASK;
}

#define NPU_SET_IFM2_WIDTH0_M1					0x0000018a
#define NPU_SET_IFM2_WIDTH0_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_IFM2_WIDTH0_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM2_WIDTH0_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_WIDTH0_M1_PARAM__SHIFT) & NPU_SET_IFM2_WIDTH0_M1_PARAM__MASK;
}

#define NPU_SET_IFM2_HEIGHT0_M1					0x0000018b
#define NPU_SET_IFM2_HEIGHT0_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_IFM2_HEIGHT0_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM2_HEIGHT0_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_HEIGHT0_M1_PARAM__SHIFT) & NPU_SET_IFM2_HEIGHT0_M1_PARAM__MASK;
}

#define NPU_SET_IFM2_HEIGHT1_M1					0x0000018c
#define NPU_SET_IFM2_HEIGHT1_M1_PARAM__MASK			0x0000ffff
#define NPU_SET_IFM2_HEIGHT1_M1_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM2_HEIGHT1_M1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_HEIGHT1_M1_PARAM__SHIFT) & NPU_SET_IFM2_HEIGHT1_M1_PARAM__MASK;
}

#define NPU_SET_IFM2_IB_START					0x0000018d
#define NPU_SET_IFM2_IB_START_PARAM__MASK			0x0000ffff
#define NPU_SET_IFM2_IB_START_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM2_IB_START_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_IB_START_PARAM__SHIFT) & NPU_SET_IFM2_IB_START_PARAM__MASK;
}

#define NPU_SET_IFM2_REGION					0x0000018f
#define NPU_SET_IFM2_REGION_PARAM__MASK				0x0000ffff
#define NPU_SET_IFM2_REGION_PARAM__SHIFT			0
static inline uint32_t NPU_SET_IFM2_REGION_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_REGION_PARAM__SHIFT) & NPU_SET_IFM2_REGION_PARAM__MASK;
}

#define NPU_SET_IFM_BASE0					0x00000000
#define NPU_SET_IFM_BASE0_RESERVED0__MASK			0x0003fffc
#define NPU_SET_IFM_BASE0_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_IFM_BASE0_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM_BASE0_RESERVED0__SHIFT) & NPU_SET_IFM_BASE0_RESERVED0__MASK;
}
#define NPU_SET_IFM_BASE0_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_IFM_BASE0_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_IFM_BASE0_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_IFM_BASE0_PAYLOAD_SIZE__SHIFT) & NPU_SET_IFM_BASE0_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_IFM_BASE1					0x00000001
#define NPU_SET_IFM_BASE1_RESERVED0__MASK			0x0003fffc
#define NPU_SET_IFM_BASE1_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_IFM_BASE1_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM_BASE1_RESERVED0__SHIFT) & NPU_SET_IFM_BASE1_RESERVED0__MASK;
}
#define NPU_SET_IFM_BASE1_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_IFM_BASE1_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_IFM_BASE1_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_IFM_BASE1_PAYLOAD_SIZE__SHIFT) & NPU_SET_IFM_BASE1_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_IFM_BASE2					0x00000002
#define NPU_SET_IFM_BASE2_RESERVED0__MASK			0x0003fffc
#define NPU_SET_IFM_BASE2_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_IFM_BASE2_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM_BASE2_RESERVED0__SHIFT) & NPU_SET_IFM_BASE2_RESERVED0__MASK;
}
#define NPU_SET_IFM_BASE2_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_IFM_BASE2_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_IFM_BASE2_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_IFM_BASE2_PAYLOAD_SIZE__SHIFT) & NPU_SET_IFM_BASE2_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_IFM_BASE3					0x00000003
#define NPU_SET_IFM_BASE3_RESERVED0__MASK			0x0003fffc
#define NPU_SET_IFM_BASE3_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_IFM_BASE3_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM_BASE3_RESERVED0__SHIFT) & NPU_SET_IFM_BASE3_RESERVED0__MASK;
}
#define NPU_SET_IFM_BASE3_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_IFM_BASE3_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_IFM_BASE3_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_IFM_BASE3_PAYLOAD_SIZE__SHIFT) & NPU_SET_IFM_BASE3_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_IFM_STRIDE_X					0x00000004
#define NPU_SET_IFM_STRIDE_X_RESERVED0__MASK			0x0003fffc
#define NPU_SET_IFM_STRIDE_X_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_IFM_STRIDE_X_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM_STRIDE_X_RESERVED0__SHIFT) & NPU_SET_IFM_STRIDE_X_RESERVED0__MASK;
}
#define NPU_SET_IFM_STRIDE_X_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_IFM_STRIDE_X_PAYLOAD_SIZE__SHIFT		0
static inline uint32_t NPU_SET_IFM_STRIDE_X_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_IFM_STRIDE_X_PAYLOAD_SIZE__SHIFT) & NPU_SET_IFM_STRIDE_X_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_IFM_STRIDE_Y					0x00000005
#define NPU_SET_IFM_STRIDE_Y_RESERVED0__MASK			0x0003fffc
#define NPU_SET_IFM_STRIDE_Y_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_IFM_STRIDE_Y_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM_STRIDE_Y_RESERVED0__SHIFT) & NPU_SET_IFM_STRIDE_Y_RESERVED0__MASK;
}
#define NPU_SET_IFM_STRIDE_Y_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_IFM_STRIDE_Y_PAYLOAD_SIZE__SHIFT		0
static inline uint32_t NPU_SET_IFM_STRIDE_Y_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_IFM_STRIDE_Y_PAYLOAD_SIZE__SHIFT) & NPU_SET_IFM_STRIDE_Y_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_IFM_STRIDE_C					0x00000006
#define NPU_SET_IFM_STRIDE_C_RESERVED0__MASK			0x0003fffc
#define NPU_SET_IFM_STRIDE_C_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_IFM_STRIDE_C_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM_STRIDE_C_RESERVED0__SHIFT) & NPU_SET_IFM_STRIDE_C_RESERVED0__MASK;
}
#define NPU_SET_IFM_STRIDE_C_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_IFM_STRIDE_C_PAYLOAD_SIZE__SHIFT		0
static inline uint32_t NPU_SET_IFM_STRIDE_C_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_IFM_STRIDE_C_PAYLOAD_SIZE__SHIFT) & NPU_SET_IFM_STRIDE_C_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_OFM_BASE0					0x00000010
#define NPU_SET_OFM_BASE0_RESERVED0__MASK			0x0003fffc
#define NPU_SET_OFM_BASE0_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_OFM_BASE0_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_OFM_BASE0_RESERVED0__SHIFT) & NPU_SET_OFM_BASE0_RESERVED0__MASK;
}
#define NPU_SET_OFM_BASE0_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_OFM_BASE0_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_OFM_BASE0_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_OFM_BASE0_PAYLOAD_SIZE__SHIFT) & NPU_SET_OFM_BASE0_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_OFM_BASE1					0x00000011
#define NPU_SET_OFM_BASE1_RESERVED0__MASK			0x0003fffc
#define NPU_SET_OFM_BASE1_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_OFM_BASE1_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_OFM_BASE1_RESERVED0__SHIFT) & NPU_SET_OFM_BASE1_RESERVED0__MASK;
}
#define NPU_SET_OFM_BASE1_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_OFM_BASE1_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_OFM_BASE1_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_OFM_BASE1_PAYLOAD_SIZE__SHIFT) & NPU_SET_OFM_BASE1_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_OFM_BASE2					0x00000012
#define NPU_SET_OFM_BASE2_RESERVED0__MASK			0x0003fffc
#define NPU_SET_OFM_BASE2_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_OFM_BASE2_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_OFM_BASE2_RESERVED0__SHIFT) & NPU_SET_OFM_BASE2_RESERVED0__MASK;
}
#define NPU_SET_OFM_BASE2_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_OFM_BASE2_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_OFM_BASE2_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_OFM_BASE2_PAYLOAD_SIZE__SHIFT) & NPU_SET_OFM_BASE2_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_OFM_BASE3					0x00000013
#define NPU_SET_OFM_BASE3_RESERVED0__MASK			0x0003fffc
#define NPU_SET_OFM_BASE3_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_OFM_BASE3_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_OFM_BASE3_RESERVED0__SHIFT) & NPU_SET_OFM_BASE3_RESERVED0__MASK;
}
#define NPU_SET_OFM_BASE3_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_OFM_BASE3_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_OFM_BASE3_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_OFM_BASE3_PAYLOAD_SIZE__SHIFT) & NPU_SET_OFM_BASE3_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_OFM_STRIDE_X					0x00000014
#define NPU_SET_OFM_STRIDE_X_RESERVED0__MASK			0x0003fffc
#define NPU_SET_OFM_STRIDE_X_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_OFM_STRIDE_X_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_OFM_STRIDE_X_RESERVED0__SHIFT) & NPU_SET_OFM_STRIDE_X_RESERVED0__MASK;
}
#define NPU_SET_OFM_STRIDE_X_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_OFM_STRIDE_X_PAYLOAD_SIZE__SHIFT		0
static inline uint32_t NPU_SET_OFM_STRIDE_X_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_OFM_STRIDE_X_PAYLOAD_SIZE__SHIFT) & NPU_SET_OFM_STRIDE_X_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_OFM_STRIDE_Y					0x00000015
#define NPU_SET_OFM_STRIDE_Y_RESERVED0__MASK			0x0003fffc
#define NPU_SET_OFM_STRIDE_Y_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_OFM_STRIDE_Y_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_OFM_STRIDE_Y_RESERVED0__SHIFT) & NPU_SET_OFM_STRIDE_Y_RESERVED0__MASK;
}
#define NPU_SET_OFM_STRIDE_Y_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_OFM_STRIDE_Y_PAYLOAD_SIZE__SHIFT		0
static inline uint32_t NPU_SET_OFM_STRIDE_Y_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_OFM_STRIDE_Y_PAYLOAD_SIZE__SHIFT) & NPU_SET_OFM_STRIDE_Y_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_OFM_STRIDE_C					0x00000016
#define NPU_SET_OFM_STRIDE_C_RESERVED0__MASK			0x0003fffc
#define NPU_SET_OFM_STRIDE_C_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_OFM_STRIDE_C_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_OFM_STRIDE_C_RESERVED0__SHIFT) & NPU_SET_OFM_STRIDE_C_RESERVED0__MASK;
}
#define NPU_SET_OFM_STRIDE_C_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_OFM_STRIDE_C_PAYLOAD_SIZE__SHIFT		0
static inline uint32_t NPU_SET_OFM_STRIDE_C_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_OFM_STRIDE_C_PAYLOAD_SIZE__SHIFT) & NPU_SET_OFM_STRIDE_C_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_WEIGHT_BASE					0x00000020
#define NPU_SET_WEIGHT_BASE_RESERVED0__MASK			0x0003fffc
#define NPU_SET_WEIGHT_BASE_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_WEIGHT_BASE_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_WEIGHT_BASE_RESERVED0__SHIFT) & NPU_SET_WEIGHT_BASE_RESERVED0__MASK;
}
#define NPU_SET_WEIGHT_BASE_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_WEIGHT_BASE_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_WEIGHT_BASE_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_WEIGHT_BASE_PAYLOAD_SIZE__SHIFT) & NPU_SET_WEIGHT_BASE_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_WEIGHT_LENGTH					0x00000021
#define NPU_SET_WEIGHT_LENGTH_RESERVED0__MASK			0x0003fffc
#define NPU_SET_WEIGHT_LENGTH_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_WEIGHT_LENGTH_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_WEIGHT_LENGTH_RESERVED0__SHIFT) & NPU_SET_WEIGHT_LENGTH_RESERVED0__MASK;
}
#define NPU_SET_WEIGHT_LENGTH_PAYLOAD_SIZE__MASK		0x00000003
#define NPU_SET_WEIGHT_LENGTH_PAYLOAD_SIZE__SHIFT		0
static inline uint32_t NPU_SET_WEIGHT_LENGTH_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_WEIGHT_LENGTH_PAYLOAD_SIZE__SHIFT) & NPU_SET_WEIGHT_LENGTH_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_SCALE_BASE					0x00000022
#define NPU_SET_SCALE_BASE_RESERVED0__MASK			0x0003fffc
#define NPU_SET_SCALE_BASE_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_SCALE_BASE_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_SCALE_BASE_RESERVED0__SHIFT) & NPU_SET_SCALE_BASE_RESERVED0__MASK;
}
#define NPU_SET_SCALE_BASE_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_SCALE_BASE_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_SCALE_BASE_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_SCALE_BASE_PAYLOAD_SIZE__SHIFT) & NPU_SET_SCALE_BASE_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_SCALE_LENGTH					0x00000023
#define NPU_SET_SCALE_LENGTH_RESERVED0__MASK			0x0003fffc
#define NPU_SET_SCALE_LENGTH_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_SCALE_LENGTH_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_SCALE_LENGTH_RESERVED0__SHIFT) & NPU_SET_SCALE_LENGTH_RESERVED0__MASK;
}
#define NPU_SET_SCALE_LENGTH_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_SCALE_LENGTH_PAYLOAD_SIZE__SHIFT		0
static inline uint32_t NPU_SET_SCALE_LENGTH_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_SCALE_LENGTH_PAYLOAD_SIZE__SHIFT) & NPU_SET_SCALE_LENGTH_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_OFM_SCALE					0x00000024
#define NPU_SET_OFM_SCALE_ROUND_MODE__MASK			0x0000e000
#define NPU_SET_OFM_SCALE_ROUND_MODE__SHIFT			13
static inline uint32_t NPU_SET_OFM_SCALE_ROUND_MODE(uint32_t val)
{
	return ((val) << NPU_SET_OFM_SCALE_ROUND_MODE__SHIFT) & NPU_SET_OFM_SCALE_ROUND_MODE__MASK;
}
#define NPU_SET_OFM_SCALE_RESERVED0__MASK			0x00001800
#define NPU_SET_OFM_SCALE_RESERVED0__SHIFT			11
static inline uint32_t NPU_SET_OFM_SCALE_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_OFM_SCALE_RESERVED0__SHIFT) & NPU_SET_OFM_SCALE_RESERVED0__MASK;
}
#define NPU_SET_OFM_SCALE_DBL_RND__MASK				0x000007c0
#define NPU_SET_OFM_SCALE_DBL_RND__SHIFT			6
static inline uint32_t NPU_SET_OFM_SCALE_DBL_RND(uint32_t val)
{
	return ((val) << NPU_SET_OFM_SCALE_DBL_RND__SHIFT) & NPU_SET_OFM_SCALE_DBL_RND__MASK;
}
#define NPU_SET_OFM_SCALE_SHIFT__MASK				0x0000003f
#define NPU_SET_OFM_SCALE_SHIFT__SHIFT				0
static inline uint32_t NPU_SET_OFM_SCALE_SHIFT(uint32_t val)
{
	return ((val) << NPU_SET_OFM_SCALE_SHIFT__SHIFT) & NPU_SET_OFM_SCALE_SHIFT__MASK;
}

#define NPU_SET_OPA_SCALE					0x00000025
#define NPU_SET_OPA_SCALE_RESERVED1__MASK			0x0000c000
#define NPU_SET_OPA_SCALE_RESERVED1__SHIFT			14
static inline uint32_t NPU_SET_OPA_SCALE_RESERVED1(uint32_t val)
{
	return ((val) << NPU_SET_OPA_SCALE_RESERVED1__SHIFT) & NPU_SET_OPA_SCALE_RESERVED1__MASK;
}
#define NPU_SET_OPA_SCALE_ROUND_MODE__MASK			0x00002000
#define NPU_SET_OPA_SCALE_ROUND_MODE__SHIFT			13
static inline uint32_t NPU_SET_OPA_SCALE_ROUND_MODE(uint32_t val)
{
	return ((val) << NPU_SET_OPA_SCALE_ROUND_MODE__SHIFT) & NPU_SET_OPA_SCALE_ROUND_MODE__MASK;
}
#define NPU_SET_OPA_SCALE_RESERVED0__MASK			0x00001800
#define NPU_SET_OPA_SCALE_RESERVED0__SHIFT			11
static inline uint32_t NPU_SET_OPA_SCALE_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_OPA_SCALE_RESERVED0__SHIFT) & NPU_SET_OPA_SCALE_RESERVED0__MASK;
}
#define NPU_SET_OPA_SCALE_DBL_RND__MASK				0x000007c0
#define NPU_SET_OPA_SCALE_DBL_RND__SHIFT			6
static inline uint32_t NPU_SET_OPA_SCALE_DBL_RND(uint32_t val)
{
	return ((val) << NPU_SET_OPA_SCALE_DBL_RND__SHIFT) & NPU_SET_OPA_SCALE_DBL_RND__MASK;
}
#define NPU_SET_OPA_SCALE_SHIFT__MASK				0x0000003f
#define NPU_SET_OPA_SCALE_SHIFT__SHIFT				0
static inline uint32_t NPU_SET_OPA_SCALE_SHIFT(uint32_t val)
{
	return ((val) << NPU_SET_OPA_SCALE_SHIFT__SHIFT) & NPU_SET_OPA_SCALE_SHIFT__MASK;
}

#define NPU_SET_OPB_SCALE					0x00000026
#define NPU_SET_OPB_SCALE_RESERVED1__MASK			0x0000c000
#define NPU_SET_OPB_SCALE_RESERVED1__SHIFT			14
static inline uint32_t NPU_SET_OPB_SCALE_RESERVED1(uint32_t val)
{
	return ((val) << NPU_SET_OPB_SCALE_RESERVED1__SHIFT) & NPU_SET_OPB_SCALE_RESERVED1__MASK;
}
#define NPU_SET_OPB_SCALE_ROUND_MODE__MASK			0x00002000
#define NPU_SET_OPB_SCALE_ROUND_MODE__SHIFT			13
static inline uint32_t NPU_SET_OPB_SCALE_ROUND_MODE(uint32_t val)
{
	return ((val) << NPU_SET_OPB_SCALE_ROUND_MODE__SHIFT) & NPU_SET_OPB_SCALE_ROUND_MODE__MASK;
}
#define NPU_SET_OPB_SCALE_RESERVED0__MASK			0x00001800
#define NPU_SET_OPB_SCALE_RESERVED0__SHIFT			11
static inline uint32_t NPU_SET_OPB_SCALE_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_OPB_SCALE_RESERVED0__SHIFT) & NPU_SET_OPB_SCALE_RESERVED0__MASK;
}
#define NPU_SET_OPB_SCALE_DBL_RND__MASK				0x000007c0
#define NPU_SET_OPB_SCALE_DBL_RND__SHIFT			6
static inline uint32_t NPU_SET_OPB_SCALE_DBL_RND(uint32_t val)
{
	return ((val) << NPU_SET_OPB_SCALE_DBL_RND__SHIFT) & NPU_SET_OPB_SCALE_DBL_RND__MASK;
}
#define NPU_SET_OPB_SCALE_SHIFT__MASK				0x0000003f
#define NPU_SET_OPB_SCALE_SHIFT__SHIFT				0
static inline uint32_t NPU_SET_OPB_SCALE_SHIFT(uint32_t val)
{
	return ((val) << NPU_SET_OPB_SCALE_SHIFT__SHIFT) & NPU_SET_OPB_SCALE_SHIFT__MASK;
}

#define NPU_SET_DMA0_SRC					0x00000030
#define NPU_SET_DMA0_SRC_RESERVED0__MASK			0x0003fffc
#define NPU_SET_DMA0_SRC_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_DMA0_SRC_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_SRC_RESERVED0__SHIFT) & NPU_SET_DMA0_SRC_RESERVED0__MASK;
}
#define NPU_SET_DMA0_SRC_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_DMA0_SRC_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_DMA0_SRC_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_SRC_PAYLOAD_SIZE__SHIFT) & NPU_SET_DMA0_SRC_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_DMA0_DST					0x00000031
#define NPU_SET_DMA0_DST_RESERVED0__MASK			0x0003fffc
#define NPU_SET_DMA0_DST_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_DMA0_DST_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_DST_RESERVED0__SHIFT) & NPU_SET_DMA0_DST_RESERVED0__MASK;
}
#define NPU_SET_DMA0_DST_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_DMA0_DST_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_DMA0_DST_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_DST_PAYLOAD_SIZE__SHIFT) & NPU_SET_DMA0_DST_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_DMA0_LEN					0x00000032
#define NPU_SET_DMA0_LEN_RESERVED0__MASK			0x0003fffc
#define NPU_SET_DMA0_LEN_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_DMA0_LEN_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_LEN_RESERVED0__SHIFT) & NPU_SET_DMA0_LEN_RESERVED0__MASK;
}
#define NPU_SET_DMA0_LEN_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_DMA0_LEN_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_DMA0_LEN_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_LEN_PAYLOAD_SIZE__SHIFT) & NPU_SET_DMA0_LEN_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_DMA0_SKIP0					0x00000033
#define NPU_SET_DMA0_SKIP0_PARAM__MASK				0x0003fffc
#define NPU_SET_DMA0_SKIP0_PARAM__SHIFT				2
static inline uint32_t NPU_SET_DMA0_SKIP0_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_SKIP0_PARAM__SHIFT) & NPU_SET_DMA0_SKIP0_PARAM__MASK;
}
#define NPU_SET_DMA0_SKIP0_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_DMA0_SKIP0_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_DMA0_SKIP0_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_SKIP0_PAYLOAD_SIZE__SHIFT) & NPU_SET_DMA0_SKIP0_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_DMA0_SKIP1					0x00000034
#define NPU_SET_DMA0_SKIP1_PARAM__MASK				0x0003fffc
#define NPU_SET_DMA0_SKIP1_PARAM__SHIFT				2
static inline uint32_t NPU_SET_DMA0_SKIP1_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_SKIP1_PARAM__SHIFT) & NPU_SET_DMA0_SKIP1_PARAM__MASK;
}
#define NPU_SET_DMA0_SKIP1_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_DMA0_SKIP1_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_DMA0_SKIP1_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_DMA0_SKIP1_PAYLOAD_SIZE__SHIFT) & NPU_SET_DMA0_SKIP1_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_OP_SCALAR					0x00000039
#define NPU_SET_OP_SCALAR_PARAM__MASK				0x0003fffc
#define NPU_SET_OP_SCALAR_PARAM__SHIFT				2
static inline uint32_t NPU_SET_OP_SCALAR_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_OP_SCALAR_PARAM__SHIFT) & NPU_SET_OP_SCALAR_PARAM__MASK;
}
#define NPU_SET_OP_SCALAR_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_OP_SCALAR_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_OP_SCALAR_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_OP_SCALAR_PAYLOAD_SIZE__SHIFT) & NPU_SET_OP_SCALAR_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_IFM2_BASE0					0x00000080
#define NPU_SET_IFM2_BASE0_RESERVED0__MASK			0x0003fffc
#define NPU_SET_IFM2_BASE0_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_IFM2_BASE0_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_BASE0_RESERVED0__SHIFT) & NPU_SET_IFM2_BASE0_RESERVED0__MASK;
}
#define NPU_SET_IFM2_BASE0_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_IFM2_BASE0_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_IFM2_BASE0_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_BASE0_PAYLOAD_SIZE__SHIFT) & NPU_SET_IFM2_BASE0_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_IFM2_BASE1					0x00000081
#define NPU_SET_IFM2_BASE1_RESERVED0__MASK			0x0003fffc
#define NPU_SET_IFM2_BASE1_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_IFM2_BASE1_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_BASE1_RESERVED0__SHIFT) & NPU_SET_IFM2_BASE1_RESERVED0__MASK;
}
#define NPU_SET_IFM2_BASE1_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_IFM2_BASE1_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_IFM2_BASE1_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_BASE1_PAYLOAD_SIZE__SHIFT) & NPU_SET_IFM2_BASE1_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_IFM2_BASE2					0x00000082
#define NPU_SET_IFM2_BASE2_RESERVED0__MASK			0x0003fffc
#define NPU_SET_IFM2_BASE2_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_IFM2_BASE2_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_BASE2_RESERVED0__SHIFT) & NPU_SET_IFM2_BASE2_RESERVED0__MASK;
}
#define NPU_SET_IFM2_BASE2_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_IFM2_BASE2_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_IFM2_BASE2_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_BASE2_PAYLOAD_SIZE__SHIFT) & NPU_SET_IFM2_BASE2_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_IFM2_BASE3					0x00000083
#define NPU_SET_IFM2_BASE3_RESERVED0__MASK			0x0003fffc
#define NPU_SET_IFM2_BASE3_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_IFM2_BASE3_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_BASE3_RESERVED0__SHIFT) & NPU_SET_IFM2_BASE3_RESERVED0__MASK;
}
#define NPU_SET_IFM2_BASE3_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_IFM2_BASE3_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_IFM2_BASE3_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_BASE3_PAYLOAD_SIZE__SHIFT) & NPU_SET_IFM2_BASE3_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_IFM2_STRIDE_X					0x00000084
#define NPU_SET_IFM2_STRIDE_X_RESERVED0__MASK			0x0003fffc
#define NPU_SET_IFM2_STRIDE_X_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_IFM2_STRIDE_X_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_STRIDE_X_RESERVED0__SHIFT) & NPU_SET_IFM2_STRIDE_X_RESERVED0__MASK;
}
#define NPU_SET_IFM2_STRIDE_X_PAYLOAD_SIZE__MASK		0x00000003
#define NPU_SET_IFM2_STRIDE_X_PAYLOAD_SIZE__SHIFT		0
static inline uint32_t NPU_SET_IFM2_STRIDE_X_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_STRIDE_X_PAYLOAD_SIZE__SHIFT) & NPU_SET_IFM2_STRIDE_X_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_IFM2_STRIDE_Y					0x00000085
#define NPU_SET_IFM2_STRIDE_Y_RESERVED0__MASK			0x0003fffc
#define NPU_SET_IFM2_STRIDE_Y_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_IFM2_STRIDE_Y_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_STRIDE_Y_RESERVED0__SHIFT) & NPU_SET_IFM2_STRIDE_Y_RESERVED0__MASK;
}
#define NPU_SET_IFM2_STRIDE_Y_PAYLOAD_SIZE__MASK		0x00000003
#define NPU_SET_IFM2_STRIDE_Y_PAYLOAD_SIZE__SHIFT		0
static inline uint32_t NPU_SET_IFM2_STRIDE_Y_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_STRIDE_Y_PAYLOAD_SIZE__SHIFT) & NPU_SET_IFM2_STRIDE_Y_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_IFM2_STRIDE_C					0x00000086
#define NPU_SET_IFM2_STRIDE_C_RESERVED0__MASK			0x0003fffc
#define NPU_SET_IFM2_STRIDE_C_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_IFM2_STRIDE_C_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_STRIDE_C_RESERVED0__SHIFT) & NPU_SET_IFM2_STRIDE_C_RESERVED0__MASK;
}
#define NPU_SET_IFM2_STRIDE_C_PAYLOAD_SIZE__MASK		0x00000003
#define NPU_SET_IFM2_STRIDE_C_PAYLOAD_SIZE__SHIFT		0
static inline uint32_t NPU_SET_IFM2_STRIDE_C_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_IFM2_STRIDE_C_PAYLOAD_SIZE__SHIFT) & NPU_SET_IFM2_STRIDE_C_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_WEIGHT1_BASE					0x00000090
#define NPU_SET_WEIGHT1_BASE_PARAM__MASK			0x0003fffc
#define NPU_SET_WEIGHT1_BASE_PARAM__SHIFT			2
static inline uint32_t NPU_SET_WEIGHT1_BASE_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_WEIGHT1_BASE_PARAM__SHIFT) & NPU_SET_WEIGHT1_BASE_PARAM__MASK;
}
#define NPU_SET_WEIGHT1_BASE_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_WEIGHT1_BASE_PAYLOAD_SIZE__SHIFT		0
static inline uint32_t NPU_SET_WEIGHT1_BASE_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_WEIGHT1_BASE_PAYLOAD_SIZE__SHIFT) & NPU_SET_WEIGHT1_BASE_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_WEIGHT1_LENGTH					0x00000091
#define NPU_SET_WEIGHT1_LENGTH_RESERVED0__MASK			0x0003fffc
#define NPU_SET_WEIGHT1_LENGTH_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_WEIGHT1_LENGTH_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_WEIGHT1_LENGTH_RESERVED0__SHIFT) & NPU_SET_WEIGHT1_LENGTH_RESERVED0__MASK;
}
#define NPU_SET_WEIGHT1_LENGTH_PAYLOAD_SIZE__MASK		0x00000003
#define NPU_SET_WEIGHT1_LENGTH_PAYLOAD_SIZE__SHIFT		0
static inline uint32_t NPU_SET_WEIGHT1_LENGTH_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_WEIGHT1_LENGTH_PAYLOAD_SIZE__SHIFT) & NPU_SET_WEIGHT1_LENGTH_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_SCALE1_BASE					0x00000092
#define NPU_SET_SCALE1_BASE_PARAM__MASK				0x0003fffc
#define NPU_SET_SCALE1_BASE_PARAM__SHIFT			2
static inline uint32_t NPU_SET_SCALE1_BASE_PARAM(uint32_t val)
{
	return ((val) << NPU_SET_SCALE1_BASE_PARAM__SHIFT) & NPU_SET_SCALE1_BASE_PARAM__MASK;
}
#define NPU_SET_SCALE1_BASE_PAYLOAD_SIZE__MASK			0x00000003
#define NPU_SET_SCALE1_BASE_PAYLOAD_SIZE__SHIFT			0
static inline uint32_t NPU_SET_SCALE1_BASE_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_SCALE1_BASE_PAYLOAD_SIZE__SHIFT) & NPU_SET_SCALE1_BASE_PAYLOAD_SIZE__MASK;
}

#define NPU_SET_SCALE1_LENGTH					0x00000093
#define NPU_SET_SCALE1_LENGTH_RESERVED0__MASK			0x0003fffc
#define NPU_SET_SCALE1_LENGTH_RESERVED0__SHIFT			2
static inline uint32_t NPU_SET_SCALE1_LENGTH_RESERVED0(uint32_t val)
{
	return ((val) << NPU_SET_SCALE1_LENGTH_RESERVED0__SHIFT) & NPU_SET_SCALE1_LENGTH_RESERVED0__MASK;
}
#define NPU_SET_SCALE1_LENGTH_PAYLOAD_SIZE__MASK		0x00000003
#define NPU_SET_SCALE1_LENGTH_PAYLOAD_SIZE__SHIFT		0
static inline uint32_t NPU_SET_SCALE1_LENGTH_PAYLOAD_SIZE(uint32_t val)
{
	return ((val) << NPU_SET_SCALE1_LENGTH_PAYLOAD_SIZE__SHIFT) & NPU_SET_SCALE1_LENGTH_PAYLOAD_SIZE__MASK;
}

#ifdef __cplusplus
#endif
static inline char *ethosu_get_cmd_name(unsigned domain, uint32_t cmd) {
    if (domain == 0 && cmd == 0x00000000) return "NPU_OP_STOP";
    if (domain == 0 && cmd == 0x00000001) return "NPU_OP_IRQ";
    if (domain == 0 && cmd == 0x00000002) return "NPU_OP_CONV";
    if (domain == 0 && cmd == 0x00000003) return "NPU_OP_DEPTHWISE";
    if (domain == 0 && cmd == 0x00000005) return "NPU_OP_POOL";
    if (domain == 0 && cmd == 0x00000006) return "NPU_OP_ELEMENTWISE";
    if (domain == 0 && cmd == 0x00000010) return "NPU_OP_DMA_START";
    if (domain == 0 && cmd == 0x00000011) return "NPU_OP_DMA_WAIT";
    if (domain == 0 && cmd == 0x00000012) return "NPU_OP_KERNEL_WAIT";
    if (domain == 0 && cmd == 0x00000013) return "NPU_OP_PMU_MASK";
    if (domain == 0 && cmd == 0x00000100) return "NPU_SET_IFM_PAD_TOP";
    if (domain == 0 && cmd == 0x00000101) return "NPU_SET_IFM_PAD_LEFT";
    if (domain == 0 && cmd == 0x00000102) return "NPU_SET_IFM_PAD_RIGHT";
    if (domain == 0 && cmd == 0x00000103) return "NPU_SET_IFM_PAD_BOTTOM";
    if (domain == 0 && cmd == 0x00000104) return "NPU_SET_IFM_DEPTH_M1";
    if (domain == 0 && cmd == 0x00000105) return "NPU_SET_IFM_PRECISION";
    if (domain == 0 && cmd == 0x00000107) return "NPU_SET_IFM_UPSCALE";
    if (domain == 0 && cmd == 0x00000108) return "NPU_SET_IFM_BROADCAST";
    if (domain == 0 && cmd == 0x00000109) return "NPU_SET_IFM_ZERO_POINT";
    if (domain == 0 && cmd == 0x0000010a) return "NPU_SET_IFM_WIDTH0_M1";
    if (domain == 0 && cmd == 0x0000010b) return "NPU_SET_IFM_HEIGHT0_M1";
    if (domain == 0 && cmd == 0x0000010c) return "NPU_SET_IFM_HEIGHT1_M1";
    if (domain == 0 && cmd == 0x0000010d) return "NPU_SET_IFM_IB_END";
    if (domain == 0 && cmd == 0x0000010f) return "NPU_SET_IFM_REGION";
    if (domain == 0 && cmd == 0x00000111) return "NPU_SET_OFM_WIDTH_M1";
    if (domain == 0 && cmd == 0x00000112) return "NPU_SET_OFM_HEIGHT_M1";
    if (domain == 0 && cmd == 0x00000113) return "NPU_SET_OFM_DEPTH_M1";
    if (domain == 0 && cmd == 0x00000114) return "NPU_SET_OFM_PRECISION";
    if (domain == 0 && cmd == 0x00000115) return "NPU_SET_OFM_BLK_WIDTH_M1";
    if (domain == 0 && cmd == 0x00000116) return "NPU_SET_OFM_BLK_HEIGHT_M1";
    if (domain == 0 && cmd == 0x00000117) return "NPU_SET_OFM_BLK_DEPTH_M1";
    if (domain == 0 && cmd == 0x00000118) return "NPU_SET_OFM_ZERO_POINT";
    if (domain == 0 && cmd == 0x0000011a) return "NPU_SET_OFM_WIDTH0_M1";
    if (domain == 0 && cmd == 0x0000011b) return "NPU_SET_OFM_HEIGHT0_M1";
    if (domain == 0 && cmd == 0x0000011c) return "NPU_SET_OFM_HEIGHT1_M1";
    if (domain == 0 && cmd == 0x0000011f) return "NPU_SET_OFM_REGION";
    if (domain == 0 && cmd == 0x00000120) return "NPU_SET_KERNEL_WIDTH_M1";
    if (domain == 0 && cmd == 0x00000121) return "NPU_SET_KERNEL_HEIGHT_M1";
    if (domain == 0 && cmd == 0x00000122) return "NPU_SET_KERNEL_STRIDE";
    if (domain == 0 && cmd == 0x00000123) return "NPU_SET_PARALLEL_MODE";
    if (domain == 0 && cmd == 0x00000124) return "NPU_SET_ACC_FORMAT";
    if (domain == 0 && cmd == 0x00000125) return "NPU_SET_ACTIVATION";
    if (domain == 0 && cmd == 0x00000126) return "NPU_SET_ACTIVATION_MIN";
    if (domain == 0 && cmd == 0x00000127) return "NPU_SET_ACTIVATION_MAX";
    if (domain == 0 && cmd == 0x00000128) return "NPU_SET_WEIGHT_REGION";
    if (domain == 0 && cmd == 0x00000129) return "NPU_SET_SCALE_REGION";
    if (domain == 0 && cmd == 0x0000012d) return "NPU_SET_AB_START";
    if (domain == 0 && cmd == 0x0000012e) return "NPU_SET_WEIGHT_FORMAT";
    if (domain == 0 && cmd == 0x0000012f) return "NPU_SET_BLOCKDEP";
    if (domain == 0 && cmd == 0x00000130) return "NPU_SET_DMA0_SRC_REGION";
    if (domain == 0 && cmd == 0x00000131) return "NPU_SET_DMA0_DST_REGION";
    if (domain == 0 && cmd == 0x00000132) return "NPU_SET_DMA0_SIZE0";
    if (domain == 0 && cmd == 0x00000133) return "NPU_SET_DMA0_SIZE1";
    if (domain == 0 && cmd == 0x00000180) return "NPU_SET_IFM2_BROADCAST";
    if (domain == 0 && cmd == 0x00000181) return "NPU_SET_IFM2_SCALAR";
    if (domain == 0 && cmd == 0x00000185) return "NPU_SET_IFM2_PRECISION";
    if (domain == 0 && cmd == 0x00000189) return "NPU_SET_IFM2_ZERO_POINT";
    if (domain == 0 && cmd == 0x0000018a) return "NPU_SET_IFM2_WIDTH0_M1";
    if (domain == 0 && cmd == 0x0000018b) return "NPU_SET_IFM2_HEIGHT0_M1";
    if (domain == 0 && cmd == 0x0000018c) return "NPU_SET_IFM2_HEIGHT1_M1";
    if (domain == 0 && cmd == 0x0000018d) return "NPU_SET_IFM2_IB_START";
    if (domain == 0 && cmd == 0x0000018f) return "NPU_SET_IFM2_REGION";
    if (domain == 1 && cmd == 0x00000000) return "NPU_SET_IFM_BASE0";
    if (domain == 1 && cmd == 0x00000001) return "NPU_SET_IFM_BASE1";
    if (domain == 1 && cmd == 0x00000002) return "NPU_SET_IFM_BASE2";
    if (domain == 1 && cmd == 0x00000003) return "NPU_SET_IFM_BASE3";
    if (domain == 1 && cmd == 0x00000004) return "NPU_SET_IFM_STRIDE_X";
    if (domain == 1 && cmd == 0x00000005) return "NPU_SET_IFM_STRIDE_Y";
    if (domain == 1 && cmd == 0x00000006) return "NPU_SET_IFM_STRIDE_C";
    if (domain == 1 && cmd == 0x00000010) return "NPU_SET_OFM_BASE0";
    if (domain == 1 && cmd == 0x00000011) return "NPU_SET_OFM_BASE1";
    if (domain == 1 && cmd == 0x00000012) return "NPU_SET_OFM_BASE2";
    if (domain == 1 && cmd == 0x00000013) return "NPU_SET_OFM_BASE3";
    if (domain == 1 && cmd == 0x00000014) return "NPU_SET_OFM_STRIDE_X";
    if (domain == 1 && cmd == 0x00000015) return "NPU_SET_OFM_STRIDE_Y";
    if (domain == 1 && cmd == 0x00000016) return "NPU_SET_OFM_STRIDE_C";
    if (domain == 1 && cmd == 0x00000020) return "NPU_SET_WEIGHT_BASE";
    if (domain == 1 && cmd == 0x00000021) return "NPU_SET_WEIGHT_LENGTH";
    if (domain == 1 && cmd == 0x00000022) return "NPU_SET_SCALE_BASE";
    if (domain == 1 && cmd == 0x00000023) return "NPU_SET_SCALE_LENGTH";
    if (domain == 1 && cmd == 0x00000024) return "NPU_SET_OFM_SCALE";
    if (domain == 1 && cmd == 0x00000025) return "NPU_SET_OPA_SCALE";
    if (domain == 1 && cmd == 0x00000026) return "NPU_SET_OPB_SCALE";
    if (domain == 1 && cmd == 0x00000030) return "NPU_SET_DMA0_SRC";
    if (domain == 1 && cmd == 0x00000031) return "NPU_SET_DMA0_DST";
    if (domain == 1 && cmd == 0x00000032) return "NPU_SET_DMA0_LEN";
    if (domain == 1 && cmd == 0x00000033) return "NPU_SET_DMA0_SKIP0";
    if (domain == 1 && cmd == 0x00000034) return "NPU_SET_DMA0_SKIP1";
    if (domain == 1 && cmd == 0x00000039) return "NPU_SET_OP_SCALAR";
    if (domain == 1 && cmd == 0x00000080) return "NPU_SET_IFM2_BASE0";
    if (domain == 1 && cmd == 0x00000081) return "NPU_SET_IFM2_BASE1";
    if (domain == 1 && cmd == 0x00000082) return "NPU_SET_IFM2_BASE2";
    if (domain == 1 && cmd == 0x00000083) return "NPU_SET_IFM2_BASE3";
    if (domain == 1 && cmd == 0x00000084) return "NPU_SET_IFM2_STRIDE_X";
    if (domain == 1 && cmd == 0x00000085) return "NPU_SET_IFM2_STRIDE_Y";
    if (domain == 1 && cmd == 0x00000086) return "NPU_SET_IFM2_STRIDE_C";
    if (domain == 1 && cmd == 0x00000090) return "NPU_SET_WEIGHT1_BASE";
    if (domain == 1 && cmd == 0x00000091) return "NPU_SET_WEIGHT1_LENGTH";
    if (domain == 1 && cmd == 0x00000092) return "NPU_SET_SCALE1_BASE";
    if (domain == 1 && cmd == 0x00000093) return "NPU_SET_SCALE1_LENGTH";
    return NULL;
}


#endif /* REGISTERS_XML */
