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To: FreeBSD-users-jp@jp.freebsd.org
From: KATO Takenori <kato@ganko.eps.nagoya-u.ac.jp>
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Subject: [FreeBSD-users-jp 54653] Re: Cyrix 486DX Cache Control on
 PC9801DA(PK-A486Cx80)
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$B2CF#!wL>Bg4d9[$G$9!%(B

KAHO Toshikazu <kaho@elam.kais.kyoto-u.ac.jp> wrote:

> $B$^$;$s!#$H$j$"$($:!"(BTroubl98.txt$B$N%Q%C%A$r;n$7$F$_$F2<$5$$!#(B

$B$3$l$r$b$H$K$$$8$C$F$_$^$7$?!%(B386$B$+$i$N%"%C%W%0%l!<%I$N>l9g!$(B
CPU_I486_ON_386$B$rIU$1$F!$%-%c%C%7%e$N%U%i%C%7%e$r9T$&I,MW$,$"$k$H;W$$(B
$B$^$9$N$G!$Cm0U$7$F$/$@$5$$!%(B


---------- BEGIN ----------
*** initcpu.c.ORIG	Mon Aug 28 15:06:11 2000
--- initcpu.c	Mon Aug 28 15:12:55 2000
***************
*** 164,169 ****
--- 164,179 ----
  #ifdef CPU_SUSP_HLT
  	ccr2 |= CCR2_SUSP_HLT;
  #endif
+ 
+ #ifdef PC98
+ 	/* Enables WB cache interface pin and Lock NW bit in CR0. */
+ 	ccr2 |= CCR2_WB | CCR2_LOCK_NW;
+ 	/* Unlock NW bit in CR0. */
+ 	write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW);
+ 	load_cr0((rcr0() & ~CR0_CD) | CR0_NW);	/* CD = 0, NW = 1 */
+ #endif
+ 
+ 
  	write_cyrix_reg(CCR2, ccr2);
  	write_eflags(eflags);
  }
***************
*** 560,565 ****
--- 570,581 ----
  			break;
  		case CPU_M1SC:
  			need_pre_dma_flush = 1;
+ 			break;
+ 		case CPU_CY486DX:
+ 			need_post_dma_flush = 1;
+ #ifdef CPU_I486_ON_386
+ 			need_pre_dma_flush = 1;
+ #endif
  			break;
  #endif
  		default:
---------- END ----------
